Many memory-bound AI applications, including natural language processing, transformer-based visual recognition, and multi-task online inference, rely heavily on large-scale general matrix-vector multiplication (GEMV), which is characterized by strong data locality. However, existing hardware architectures for AI model inference face significant data transfer overheads and fail to fully exploit the data locality inherent in these algorithms. We propose a scalable one-logic-two-DRAM (1L2D) multi-core near-DRAM computing accelerator based on 3D hybrid bonding for AI models. Our 3D integration of RISC-V processors with vector accelerators and DRAM presents a unique approach that significantly boosts bandwidth while reducing energy consumption. A memory access circuit supporting page hit mechanism and prefetching strategy is designed to maximize the utilization of the data locality achieved by the algorithm's partitioning and rearranging of data. An interleaving memory address mapping scheme is designed to effectively enhance the bank-level parallelism of data access. Compared with the high-performance Intel Xeon-6230 CPU and the state-of-the-art commercially available UPMEM-PIM, the proposed architecture's computational efficiency for large-scale GEMV is improved by 3.4× and 2.2×, respectively. The architecture achieves a 3.07× improvement in bandwidth and a 76% reduction in energy consumption over the HBM2-PIM.

Brillouin optical correlation-domain reflectometry (BOCDR) enables distributed strain and temperature measurements along optical fibers with high spatial resolution and random-access capability. Conventional BOCDR setups typically require sinusoidal laser frequency modulation, achieved either by direct or external modulation. In external modulation, double-sideband modulators (DSBMs) are generally used, but one of the sidebands must be discarded using narrowband optical filtering. Here, we propose and experimentally validate an approach that replaces the DSBM with a single-sideband modulator, eliminating the need to discard a sideband. We demonstrate efficient single-sideband modulation in BOCDR and apply the technique to measure the temperature distribution in a 100 m silica fiber.

Reproducing realistic vibrohaptic sensations in virtual reality (VR) remains challenging due to the limitations of consumer-grade actuators and SDKs. This study proposes a perceptually grounded framework that enables the presentation of realistic vibration sensations using standard VR devices, specifically the Meta Quest 3. In the case of high-frequency signals, we apply intensity segment modulation (ISM), which converts signals such as speech and recorded vibrations into amplitude modulation waveforms that maintain the perceived intensity, based on a psychophysical model of haptic intensity. By experimentally mapping the relationship between SDK parameters and the actual vibration characteristics (frequency and amplitude), we enabled accurate control of vibration strength. Furthermore, the results of the vibration measurements confirmed that the high-frequency vibration of the intended amplitude envelope could be reproduced. For low-frequency sensations, we applied a pulse-based proxy method by utilizing short-duration pulse inputs. By leveraging specific SDK functionality, we were able to reproduce single-cycle pulse vibrations, and confirmed through physical measurements that the resulting actuator response generated residual vibrations consistent with the intended low-frequency haptic impressions. In addition to physical measurements, we conducted user studies to evaluate the perceptual quality of the reproduced vibrations. For high-frequency stimuli, we compared ISM-based vibrations delivered by the VR controller with those from a high-fidelity actuator and found that the perceptual impressions were comparable. For low-frequency stimuli, participants evaluated proxy vibrations based on pulse input, and results indicated that the perceived differences from the original vibrations were small when appropriate pulse frequencies were used. These findings demonstrate that perceptually realistic haptic feedback across a broad frequency range can be achieved using perceptually motivated signal transformation methods and commercial VR hardware, without the need for specialized actuators.

This paper presents a design method for a wideband multimode primary horn by controlling the wavefront on the aperture. This approach minimizes frequency-dependent variations in gain and beamwidth through curved taper optimization. As a design example, we present a spline-profile horn antenna optimized over a frequency range of 9-16 GHz (fractional bandwidth 56 %), achieving rotationally symmetrical radiation patterns with minimal variations in beamwidth and gain.

Adiabatic quantum-flux-parametron (AQFP), a superconductor logic system, has the potential to achieve 10⁴-10⁵ times greater energy e!ciency than advanced CMOS while operating at several gigahertz clock frequencies. However, it requires improved circuit density. Approximate computing, a novel computing paradigm, reduces complexity and power consumption at the expense of accuracy, and is aimed at applications that can tolerate certain levels of faults. Hence, employing approximate computing in the design of AQFP arithmetic circuits not only enables further reduction in power consumption but also improves circuit density. In this study, we introduce two 2-bit approximate adders with different architectures, primarily utilizing three-input and five-input majority gates, which are compatible with the existing AQFP standard cell library. Our designs aim to reduce circuit complexity while maintaining a reasonable level of accuracy. The performance of these designs is evaluated based on multiple criteria, including Josephson junction (JJ) counts, circuit delays, energy, and error metrics. Our MAJ35AA design, composed of both a three-input majority gate and a five-input majority gate, shows superior hardware performance. It achieves a reduction of approximately 15% in JJ counts compared to the existing state-of-the-art approximate design. Furthermore, our design achieves a maximum absolute error (MAE) of 1 and a normalized mean error distance (NMED) of 0.0714, indicating that its accuracy level is equivalent to that of the state-of-the-art designs. We fabricated this design using the AIST 10 kA/cm² high-speed standard process (HSTP) and validated its functionality through cryogenic measurements.

In CRYSTALS-Kyber, polynomial multiplication is the most time-consuming and critical operation, presenting a challenge of balancing between speed and resource utilization. In this paper, We propose a configurable, resource-efficient, and high-speed polynomial multiplier. First, we propose an interactive-port based butterfly unit for Number Theoretic Transform (NTT), Inverse NTT (INTT), and Polynomial Multiplication (PM). We reduce processing stages from four to two by employing the Karatsuba algorithm for PM leading to 47% reduction with respect to computational cycles. Secondly, we propose a Barrett reduction module based on hardware-friendly lookup-table. By segmenting the data into smaller 2-bit widths and utilizing the binary property of modulus, we reduce the DSP consumption and the delay. Lastly, we design a modular adder/subtractor that is merged with division-by-2 operation through the implementation of streamlined digital logic, leading to a shorter INTT operation cycles. Our proposed multiplier is implemented on the Xilinx Artix-7 platform, achieving a frequency of 277MHz. Experimental results indicate that our polynomial multiplier outperforms state-of-the-art works, reducing the Area-Time Product (ATP) by 22.3%.

In this work, wideband radio-frequency (RF) bi-directional couplers with phase shifters (PS) for low insertion loss are presented. Conventional narrowband directional couplers have limited bandwidth because of excessive power loss due to strong coupling at high frequencies. To alleviate this issue, a directional coupler employing a phase shifter has been proposed. However, the analytical equation of main-line insertion loss has not been derived so far. The insertion loss equations for a coupler consisting of two coupled lines and one phase shifter is derived and presented. To achieve further loss reduction, we propose a coupler in which the coupled lines are divided into three sections and two phase shifters are inserted. Simulation and measurement results confirm that the coupler with two phase shifters achieves significantly lower insertion loss (IL) at high frequencies and enables broadband operation.

We experimentally observed modal interference spectra over a broad wavelength range in polymethyl methacrylate (PMMA)-based polymer optical fibers (POFs) and then investigated their strain dependence. At around 1550 nm, we obtained a wavelength shift of about -17 nm/% under applied strain, representing the strongest sensitivity within the spectral range covered. We infer that the critical wavelength lies above 1600 nm, and by also considering the wavelength dependence of propagation loss, we established guidelines for selecting the optimal wavelength region when implementing PMMA-POF-based strain sensors.

Silicon spin qubits are a promising technology for scalable quantum computing, leveraging their inherent compatibility with CMOS integration process. However, as the number of silicon spin qubits increases, the exponential growth in signal cables required to control qubits within a dilution refrigerator become a significant bottleneck, along with the thermal inflow from external control systems. In addition, the implementation of signal wiring for qubit chips with a large number of I/O pads and internal heat generation of qubits themselves are also barriers to scale-up. To address these issues, we have developed cryogenic CMOS (Cryo-CMOS) analog circuits and advanced chip packaging techniques at deep cryogenic temperatures inside the refrigerator. These techniques enable the implementation of extensive signal wiring while suppressing heat generation, contributing to the realization of large-scale silicon spin qubit control. In this paper, we introduce cryogenic analog circuit designs including digital-to-analog converter (DAC) and analog-to-digital converter (ADC) for biasing spin qubits and acquiring their environmental data, respectively, with a focus on low power consumption and small area to meet space and power budget within the refrigerator. Furthermore, we introduce cryogenic flip-chip packaging techniques using silicon interposer and Cu-Cu bonding technology to enhance heat dissipation as examples of packaging strategies for installing large-scale qubit chips. These proposed techniques have been implemented as prototype chips, and their effectiveness has been demonstrated through cryogenic experiments using refrigerators.

A fractional-order sliding mode speed control strategy based on the improved generalized super-twisting algorithm (FO-IGSTA-SMC) is proposed for the Permanent Magnet Synchronous Motor (PMSM), which is sensitive to load disturbances and parameter variations. First, the PMSM motion equation is utilized to construct the fractional-order sliding mode surface according to its speed error. Second, fractional-order sliding mode control (FOSMC) is combined with the improved generalized super-twisting algorithm (IGSTA) to mitigate chattering phenomenon and enhance system robustness. Finally, the effectiveness and feasibility of the proposed strategy are validated through simulations.

This paper proposes a novel system design and configuration for ultra-wideband transmission using channel bonding (CB) in sub-terahertz bands. In the CB transmission system, a transmitter generates a frequency-multiplexed signal using multiple narrowband channels, and a receiver separates individual narrowband channels from the frequency-multiplexed signal. In principle, CB transmission achieves a transmission data rate proportional to the number of multiplexed channels. However, insufficient isolation characteristics between bonded channels reduce the achievable transmission data rate with multiple channels. To address this, the proposed configuration prevents the reduction in the transmission data rate caused by power leaked to the other channels when increasing the number of bonded channels. To demonstrate a high transmission data rate, a prototype transmission system that transmits a CB signal comprising four channels with a bandwidth of 2.1 GHz each is designed and constructed based on the proposed configuration. Real-time transmissions with a total transmission data rate exceeding 100 Gbps are successfully achieved in a line-of-sight communication environment over a distance of 40 m employing three transmission systems operated in 120-GHz, 130-GHz, and 140-GHz bands each.

In order to address issues such as stator current distortion and increased harmonics caused by the dead-time effect in power devices of permanent magnet synchronous motorized spindle (PMSMS), a sensorless control strategy with dead-time compensation based on an adaptive linear neuron (ADALINE) neural network bandpass filter (NNBPF) is proposed. First, this paper introduces a neural network extended state observer phase-locked loop (NNESO-PLL) based on NNBPF, in conjunction with a stator flux observer to realize a position sensorless control strategy capable of suppressing high-order harmonics. Second, NNBPF is utilized to extract 5th and 7th harmonic components of α-β axis currents, and the least mean square (LMS) algorithm is employed to adaptively adjust the weights. The modulated linear neuron output vector serves as feedforward compensation voltage, aiming to suppress current harmonics and mitigate the impact of the dead-time effect. Finally, the proposed sensorless and dead-time compensation sensorless control strategy is compared with traditional sensorless control methods under the influence of dead-time effects. Experimental results verify that the proposed strategy effectively suppresses current harmonics, reduces current distortion, and achieves stable rotor speed tracking.

A method was proposed by the authors to shorten duration of break arcs by ejecting airflow from an electrical contact surface into a contact gap. The effect of the airflow to shorten the arc duration was confirmed by experiments. However, since it was impossible to measure the airflow in the contact gap, its distribution was unknown. Therefore, numerical analyses of airflow distribution between the electrical contacts are performed. In this paper, analyzed results are shown for different contact geometries with different diameters of airflow holes. The analyzed results of the airflow in contact gaps are used to discuss experimental results. Following results are shown. When the airflow hole is larger, sufficient airflow velocity toward the outside in the radial direction is maintained near the opposed contact surface. For the case of smaller hole, the velocity distribution toward the outside in the radial direction exists only in the thin layer close to the opposed contact surface and the maximum airflow velocity is slower. The analyzed results confirm that the faster and thicker airflow efficiently pushes out the break arc for the case of larger hole, which shortens the arc duration.

Radio frequency (RF) integrated circuits for wireless applications began evolving in the 1990s, with the second generation of mobile phones as the primary application. The wireless local area network (WLAN), which began in the 2000s, and the fourth-generation mobile phone (smart phone), which began in the 2010s, have greatly expanded the transmission volume.

The fifth generation of cell phones, which began in the 2020s, expanded the adaptive band to the millimeter wave band. The 6th generation mobile phones, which are expected to start in the 2030s, will continue to evolve to higher frequency bands, including sub-THz, for further expansion of transmission capacity. After the 4th generation, the application is not only for mobile phones but also for the IoT and other applications. Therefore, the required characteristics are also diverse, including broadband high-capacity transmission and narrow bandwidth low power consumption. This paper describes the evolution of integrated circuits for wireless applications, focusing on data communications, especially on high-capacity applications.

An energy-efficient 2-read/write (2RW) dual-port (DP) SRAM with a new disturbance aware replica scheme has been demonstrated. This scheme aims to generate internal critical timing signals for sense-enable (SE) triggers and wordline (WL) negating paths during the readout operation. By placing individual replica circuits for each port, appropriate internal delays are generated self-adjustably, whether accessing same-row or different-row. Even when the two clock inputs have different phases and frequencies, the proposed replica circuit effectively generates internal timings by mimicking the discharge speeds of each bitline (BL) using replica 8T DP bitcells. A prototype of a 256-kbit DP SRAM macro has been implemented in 90 nm logic CMOS technology. Measurement results show that the dynamic power consumption in the cell array is reduced by 16.6% compared to the conventional replica scheme at a typical supply voltage of 1.2 V and room temperature.

This paper is devoted to H_∞ state feedback control for closed-loop active magnetic bearing (AMB) system with delays. To suppress disturbances in the system, state-space model of closed-loop AMB system including outside disturbances and delays is established for stability analysis and controller design. The delays of all components are defined as a bounded time-varying function. Then Wirtinger inequality and convex inequality are used to deal with the integral term caused by delays. Through a separating technique technique, the constraint relationship between the controller gain, system matrices and the Lyapunov variables is eliminated. Based on these strategies, new sufficient conditions for the stability of closed-loop AMB system with delays and disturbances are formulated in the framework of linear matrix inequalities. Finally, the effectiveness of the proposed H_∞ state feedback controller is validated on a closed-loop AMB system.

We study how to optimize the coupling efficiency between silicon nitride and silicon waveguides using an edge coupler with an inverse-tapered structure, specifically targeting broad bandwidth applications. Initially, we hypothesized that mode matching alone would suffice for effective coupling. However, our results indicate that maximizing the coupling efficiency requires the simultaneous optimization of mode coupling and effective refractive-index matching. Theoretical simulations predicted a maximum coupling efficiency of 0.963, while experimental measurements yielded an efficiency of 0.588. We analyzed the wavelength dependence of our coupler, and found that the edge coupler exhibited broader bandwidth properties than a standard multilayer coupler, making it more suitable for applications across a wide wavelength range. These results indicate the potential for integrating such couplers with microresonator frequency comb systems, offering the possibility of a wide range of photonic applications.

Aiming at the problem of high common-mode voltage in active midpoint clamp (ANPC) three-level three-phase four-bridge inverter topology, a common-mode voltage suppression strategy based on carrier reversal is proposed, which can suppress common-mode voltage (CMV) under different operating conditions. The influence factors of CMV and the influence law of carrier change on CMV are analyzed, and the effect of reverse carrier modulation strategy on suppressing CMV is proved. The new modulation strategy proposed in this paper is a further improvement on the traditional reverse carrier modulation strategy. This suppression strategy can effectively reduce the CMV peak and switching times, but does not occupy additional dsp computing resources. Finally, the feasibility and effectiveness of the proposed method are verified on the experimental platform.

For integrated circuit design, optimizing circuit parameters is crucial to achieve wide operating margins and high yields, even in the presence of fluctuations and variations in device characteristics. In this paper, we report the development of a new circuit parameter optimization tool for superconductor integrated circuits, leveraging the latest analog circuit simulator and the center of gravity method. The developed optimization tool, implemented in C++, utilizes a parallel processing algorithm for highspeed optimization. By using only the phase information of the Josephson junction to distinguish the correct behavior of the circuit, this tool can be applied not only to conventional single flux quantum (SFQ) circuits but also to superconductor circuits whose behavior is not based on a 2π phase change. We optimized several SFQ logic gates and compared the margin expansion and optimization time with conventional optimization tools. Our tool achieved an optimization time of less than 2% of that of conventional tools in most cases. This optimization tool facilitates the rapid parameter optimization of any superconductor circuits containing various types of Josephson junctions.

The Agile Earth Observation Satellite Constellations Mission Planning (AEOSCMP) problem seeks to maximize global cumulative reward by optimizing task selection and scheduling across the Earth's surface while adhering to the intricate resource constraints of individual satellites. This optimization challenge is further complicated by the diverse observation intervals required for different targets and the necessity for coordinated action among multiple satellites, introducing complexities in synchronization, data consistency, and overall mission planning. Deep reinforcement learning (DRL) and target clustering represent two complementary methodologies that synergistically enhance the autonomy and observation efficiency of AEOSCMP. This letter introduces an innovative approach that elegantly unifies these two methodologies - the Integrated Clustering and Planning with Proximal Policy Optimization Algorithm (ICP3O). This sophisticated framework seamlessly preserves the intelligent decision-making capabilities inherent to DRL while delivering substantial improvements in observation efficiency.

The growing interest in interleaved digital-to-analog converters (DACs) has led to numerous developments and designs, while extending interleaving factors poses several challenges. This research presents a hybrid segment architecture for expanding the number of channels in time-interleaved (TI)-DACs, addressing critical limitations of existing architectures. Our architecture incorporates a pre-filter, a single-stage analog multiplexer, and an output combiner, enabling improved performance and compromising bandwidth and usable output swing. In addition, a comprehensive system-level analysis is conducted in this paper to evaluate the performance of different TI-DAC architectures. The simulation result highlights the effectiveness of the hybrid architecture in achieving superior SNR with sufficient bandwidth and overcoming the challenges of channel number extension.

In a 100VDC/10A resistive circuit, break arcs are generated between electrical contacts. Silver electrical contacts with airflow ejection structure are separated at a constant speed. The duration and motion of the break arcs are investigated for different contact shapes. Three types of contact shapes are used. Contact diameters and airflow hole diameters are changed. Following results are shown. An effective shape of the contacts was found to shorten the arc duration. The arc duration was shortened by decreasing the diameter of the contacts and increasing the diameter of airflow hole for the airflow ejection. The results are discussed in terms of the motion characteristics of the cathode spots on the cathode surface and the shapes of the break arcs.

In this work, an 8-bit signed approximate adder (SAA) and a quantization- and bit-pruning-aware training method (QBAT) are proposed to reduce the substantial area and power consumption caused by adder trees for digital Computation-in-Memory (DCiM). QBAT achieves efficient bit pruning and minimizes the accuracy loss caused by the approximation. The SAA reduce area and power consumption by 20% and power-delay product (PDP) by 36.7%. With QBAT, the proposed design achieves 95.5% and 96.4% inference accuracy for Resnet-18 and Resnet-50 models on the CIFAR-10 dataset.

We propose a configuration for Brillouin optical correlation-domain reflectometry (BOCDR) in which the electrical signal processing unit is placed remotely and connected to the optical measurement unit via a long-distance optical fiber. This arrangement eliminates the need for bulky electrical devices at the measurement site. We investigate the effect of changing the connecting fiber length and demonstrate that Brillouin frequency shift distributions can be obtained with separations of up to approximately 20 km under the tested conditions. We also show the importance of compensating for propagation losses when using long-distance fibers.

This paper presents a CMOS full-wave switching rectifier capable of mixer operation. The proposed CMOS switching rectifier allows DC power generation and frequency conversion without a power supply. The proposed CMOS switching rectifier using a center-tapped balun produces DC power with 40.7 % efficiency, while at the same time providing frequency up-conversion with -16.4 dB and down-conversion with -10.8 dB. The size of the chip is 0.286mm², and four chips are mounted on the phased-array antenna board. The board can be used as a wirelessly powered relay transceiver, and the relay transceiver can be driven without an external power supply. In TX mode, the beamwidth is narrower than that of a common phased array transceiver, but it is capable of beam steering from -45 to 45 degrees. On the other hand, in RX mode, the wide beamwidth allows the proposed relay transceiver to receive from a wide range without changing the phase shifter settings. The measured EVM values are -27.4dB for TX mode and -27.5dB for RX mode with a 400-MHz 64QAM OFDMA-mode signal (5G NR, MCS 17).

A low-power rectifier for RF energy harvesting based on a novel operating principle is presented. The proposed diode rectifier integrates an external series inductor that resonates with the diode's parasitic capacitances. This resonance enhances the electromotive force of the inductor, amplifying the RF input signal. As a result, the finite threshold voltage of silicon-based Schottky barrier diodes (SBDs) is effectively reduced, improving their sensitivity to weak environmental RF signals. Prototype rectifiers designed to operate at single and multiple resonant frequencies were fabricated using commercial discrete SBDs. These prototypes exhibited notably high RF-to-DC power conversion efficiencies at an RF input power of -20 dBm, achieving, for example, 38% efficiency at 700MHz and an average efficiency of 21.6% across the 0.43-0.77 GHz band.

This paper proposes a design method for a decoupling network between antennas using a patch antenna array as a resonator, aimed at reducing network components. A key challenge in utilizing a patch antenna array as a resonator is the narrow spacing between transmission admittance inversion poles between antennas, leading to narrowband isolation. To address this issue, the study focused on the phase of even and odd modes of the patch antenna and successfully widened the spacing between the inversion poles of the transmission admittance by connecting a transmission line of appropriate length to the antenna. As a result, isolation with two transmission zeros was achieved without the need for an external resonator.

This paper presents a millimeter-wave transceiver front-end (FE) circuit including a power amplifier (PA), a low noise amplifier equipped with phase inverter (LNA-PI), and a transmission/reception switch (TRX-SW) fabricated in 0.13-μm SiGe BiCMOS. The TRX-SW is configured as the output matching network for the PA in TX mode and as the input matching network for the LNA-PI in RX mode. The PA is implemented using a three stacked transistors architecture to provide high output power. Measurements of the FE in TX mode demonstrate peak S₂₁ of 33.0 dB at 29.9 GHz, S₂₁ 3-dB bandwidth (BW_-3dB) of 14.5 GHz from 18.0 to 32.5 GHz, saturated output power above 21 dBm, and power-added efficiency of 16.9 to 20.5% from 24 to 30 GHz. The PA achieves a competitive ITRS FoM of 96.3. In RX mode, the FE demonstrate peak S₂₁ of 23.4 dB at 20.0 GHz, S₂₁ BW_-3dB of 14.6 GHz from 18.2 to 32.8 GHz, and noise figure lower than 4 dB. The PI shows 180° phase shift within 10% error.

Low-noise, low-current consumption, and high-linearity 920-MHz fully-integrated cascode LNA operated under moderate-inversion region is presented. To obtain low-noise characteristics using an integrated poor-Q-factor on-chip inductor, a transistor operating under moderate inversion was found to be optimal since the inductance of the input inductor can be reduced. Furthermore, the moderate inversion operation presents low current consumption. However, the odd-order transconductance of the MOSFET operating under the moderate-inversion region induced poor linearity, which improved the gate width and gate bias optimization of the cascode MOSFET. The measurement results include an |s₂₁| of 14.0 dB, NF of 2.10 dB, and -5.2 dBm IIP3 with current consumption of 1.6 mA. The process technology used in this study was the TSMC 180 nm CMOS technology.

A cryogenic analog controller (CAC) for a silicon quantum computer using a spin qubit is presented in this paper, which operates on 4-K plate in a dilution refrigerator to suppress heat flow to qubits and latency. An RF pulse generator is a key for precise control of a spin qubit in CAC, which is required to generate 20-GHz pulse with low phase error. A low-noise LO and calibrations for DC offset and IQ imbalance are implemented in the pulse generator. LO includes LDO operating at weak inversion region and transformer coupled VCO cores to suppress flicker noise. A BGR operating at weak inversion region is also applied to supply low-noise bias voltage. CAC including the pulse generator is fabricated in 40-nm CMOS process. Low LO jitter of 137.4 fs, -59.7-dBc LO leakage, 67.7-dB IRR and 388-nJ energy per quantum operation have been achieved with the proposed 20-GHz LO and calibrations, resulting in 99.93-% fidelity.

A novel gain and maximum oscillation frequency (fmax) enhancement method for GaN high-electron-mobility transistors (HEMTs) was developed using a standing wave-controlled gate (SC-gate). By intentionally modifying the fingertip termination condition, drastic gain and fmax improvements were achieved in the millimeter-wave frequency band without changing the manufacturing process of the GaN HEMTs. This study reviews the SC-gate technology and previous prototype evaluation results and reports additional analysis results. Furthermore, a W-band amplifier, MMIC, was designed and fabricated based on the S-parameter measurement data of the SC-gate GaN HEMT. The maximum available gain (MAG) of the SC-gate GaN HEMT used in this amplifier MMIC was 10 dB at 80 GHz, whereas the MAG in a conventional GaN HEMT without an SC-gate was 4.5 dB. The maximum gain of the fabricated amplifier MMIC was 6.3 dB at 80.6 GHz. This value is higher than that of the conventional GaN HEMT, which confirms the effectiveness of the SC-gate technology in the W band.

Two-dimensional electron gases (2DEGs) are essential not only for modern electronics but also for the advancement of next-generation communication technologies and quantum computing. Here, we report a non-contact method for characterizing material parameters of 2DEGs using circularly polarized TE_11n modes. By developing an excitation method utilizing a circular patch antenna with an adjustable coupling hole, we enable the use of higher-order modes up to TE₁₁₇, while minimizing the effects of cylindrical symmetry breaking. This method is demonstrated by measuring the magnetic field dependence of microwave conductivities in a GaAs/AlGaAs heterojunction at 300 K and 77 K. The electron mobility obtained by fitting to the Drude model is in good agreement with the results from standard Hall measurements. Additionally, the signature of cyclotron resonance is clearly observed at 77 K, and the effective electron mass is successfully estimated. The present method could accelerate fundamental research and device development using various 2DEGs.

In this paper, we propose a sensor node using a unidirectional harmonic antenna that can acquire remote sensor information without complex digital circuits. The antenna suitable for the harmonic sensor node is characterized by utilizing a wideband E-shaped element to suppress pattern degradation at harmonic frequencies. First, through basic investigations where the sensor is modeled as a variable voltage source, we demonstrate that sensor voltage information can be remotely detected based on the transmission zero frequency. Next, using a sensor node incorporating a temperature sensor and energy harvesting circuit as an example, we show that the temperature in a remote location can be detected from the stopband frequency, thereby verifying the effectiveness of the proposed method. These findings are validated through harmonic balance analysis, electromagnetic field simulations, and RF circuit simulations.

This paper presents topology optimization of microstrip lines using twin deep neural networks (DNNs) for prediction of scattering parameters and its accuracy evaluation. Topology optimization can be accelerated by using a DNN that acts as a surrogate model for time-consuming EM simulations. However, if the prediction accuracy of the DNN for performance prediction is not high enough, the optimization will fail due to misleading caused by prediction errors. To reduce the risk of optimization failure, the present method introduced an additional DNN to evaluate the accuracy of the performance prediction. The proposed method is shown to be effective in avoiding misleading and speeding up the optimization process through numerical and experimental results.

In this paper, we have investigated the integration process at room temperature and device characteristics of 1 transistor type nonvolatile memory with organic semiconductor field-effect transistor (OFET) integrated with resistive random access memory (ReRAM). The threshold voltage (V_TH) of pentacene-based OFET with LaB_xN_y gate insulator is controlled by the ReRAM characteristics of LaB_xN_y gate insulator. The bottom-gate type pentacene-based OFET was fabricated on SiO₂/Si(100) substrate. The nitrogen-doped LaB₆ bottom gate electrode was deposited by RF sputtering and patterned. Then, LaB_xN_y gate insulator was deposited by the RF sputtering followed by the pentacene and Au source and drain electrode deposition by the evaporation. The Set/Reset operations of ReRAM were confirmed by the drain voltage sweep of ± 2 V. Furthermore, V_TH shift of -0.9 V was observed by the Set operation of ReRAM so that the nonvolatile memory characteristics were realized for the 1 transistor type ReRAM/OFET.