Design and Impact on ESD/LU Immunities by Drain-Side Super-Junction Structures in Low-(High-)Voltage MOSFETs for the Power Applications

Abstract

In this study, the reference pure metal-oxide semiconductor field-effect transistors (MOSFETs) and low-voltage (LV) and high-voltage (HV) MOSFETs with a super-junction (SJ) structure in the drain side were experimentally compared. The results show that the drain-side engineering of SJs exerts negative effects on the electrostatic discharge (ESD) and latch-up (LU) immunities of LV n-channel MOSFETs, whereas for LV p-channel MOSFETs and HV n-channel laterally diffused MOSFETs (nLDMOSs), the effects are positive. Compared with the pure MOSFET, electrostatic discharge (ESD) robustness (I_t2) decreased by approximately 30.25% for the LV nMOS-SJ, whereas I_t2 increased by approximately 2.42% and 46.63% for the LV pMOS-SJ and HV nLDMOS-SJ, respectively; furthermore, LU immunity (V_h) decreased by approximately 5.45% for the LV nMOS-SJ, whereas V_h increased by approximately 0.44% and 35.5% for the LV pMOS-SJ and HV nLDMOS-SJ, respectively. Thus, nMOS-SJ (pMOS-SJ and nLDMOS-SJ) has lower (higher) I_t2 and V_h, and this drain-side SJ structure of MOSFETs is an inferior (superior) choice for improving the ESD/LU reliability of LV nMOSs (LV pMOS and HV nLDMOS).