Regular Section
Low Complexity and Low Power Sense-Amplifier Based Flip-Flop Design
2019 年 E102.C 巻 11 号 p. 833-838
詳細
2019 年 E102.C 巻 11 号 p. 833-838
A novel low power sense-amplifier based flip-flop (FF) is presented. By using a simplified SRAM based latch design and pass transistor logic (PTL) circuit scheme, the transistor-count of the FF design is greatly reduced as well as leakage power performance. The performance claims are verified through extensive post-layout simulations. Compared to the conventional sense-amplifier FF design, the proposed circuit achieves 19.6% leakage reduction. Moreover, the delay, and area are reduced by 21.8% and 31%, respectively. The performance edge becomes even better when the flip-flop is integrated in N-bit register file.
