IEICE Transactions on Electronics
Online ISSN : 1745-1353
Print ISSN : 0916-8524
E102.C 巻, 11 号
選択された号の論文の12件中1~12を表示しています
Special Section on Electronic Displays
Regular Section
  • Kyo INOUE
    原稿種別: PAPER
    専門分野: Lasers, Quantum Electronics
    2019 年 E102.C 巻 11 号 p. 818-824
    発行日: 2019/11/01
    公開日: 2019/11/01
    [早期公開] 公開日: 2019/06/07
    ジャーナル 認証あり

    Phase-sensitive amplification (PSA) has unique properties, such as the quantum-limited noise figure of 0 dB and the phase clamping effect. This study investigates PSA characteristics when a chirped pulse is incident. The signal gain, the output waveform, and the noise figure for an optical pulse having been chirped through chromatic dispersion or self-phase modulation before amplification are analyzed. The results indicate that the amplification properties for a chirped pulse are different from those of a non-chirped pulse, such that the signal gain is small, the waveform is distorted, and the noise figure is degraded.

  • Lu TANG, Zhigong WANG, Tiantian FAN, Faen LIU, Changchun ZHANG
    原稿種別: PAPER
    専門分野: Electronic Circuits
    2019 年 E102.C 巻 11 号 p. 825-832
    発行日: 2019/11/01
    公開日: 2019/11/01
    [早期公開] 公開日: 2019/06/07
    ジャーナル 認証あり

    In this paper, an improved charge pump (CP) and a modified nonlinear phase frequency detector (PFD) are designed and fabricated in a 90-nm CMOS process. The CP is optimized with a combination of circuit techniques such as pedestal error cancel scheme to eliminate the charge injection and the other non-ideal characteristics. The nonlinear PFD is based on a modified circuit topology to enhance the acquisition capability of the PLL. The optimized CP and nonlinear PFD are integrated into a Ka-band PLL. The measured output current mismatch ratio of the improved CP is less than 1% when the output voltage Vout fluctuates between 0.2 to 1.1V from a 1.2V power supply. The measured phase error detection range of the modified nonlinear PFD is between -2π and 2π. Owing to the modified CP and PFD, the measured reference spur of the Ka-band PLL frequency synthesizer containing the optimized CP and PFD is only -56.409dBc at 30-GHz at the locked state.

  • Po-Yu KUO, Chia-Hsin HSIEH, Jin-Fa LIN, Ming-Hwa SHEU, Yi-Ting HUNG
    原稿種別: PAPER
    専門分野: Electronic Circuits
    2019 年 E102.C 巻 11 号 p. 833-838
    発行日: 2019/11/01
    公開日: 2019/11/01
    [早期公開] 公開日: 2019/08/05
    ジャーナル 認証あり

    A novel low power sense-amplifier based flip-flop (FF) is presented. By using a simplified SRAM based latch design and pass transistor logic (PTL) circuit scheme, the transistor-count of the FF design is greatly reduced as well as leakage power performance. The performance claims are verified through extensive post-layout simulations. Compared to the conventional sense-amplifier FF design, the proposed circuit achieves 19.6% leakage reduction. Moreover, the delay, and area are reduced by 21.8% and 31%, respectively. The performance edge becomes even better when the flip-flop is integrated in N-bit register file.

  • Kotchakorn PITUSO, Chanon WARISARN, Damrongsak TONGSOMPORN
    原稿種別: PAPER
    専門分野: Storage Technology
    2019 年 E102.C 巻 11 号 p. 839-844
    発行日: 2019/11/01
    公開日: 2019/11/01
    [早期公開] 公開日: 2019/08/05
    ジャーナル フリー

    When the track density of two-dimensional magnetic recording (TDMR) systems is increased, intertrack interference (ITI) inevitably grows, resulting in the extreme degradation of an overall system performance. In this work, we present coding, writing, and reading techniques which allow TDMR systems with multi-readers to overcome severe ITI. A rate-5/6 two-dimensional (2D) modulation code is adopted to protect middle-track data from ITI based on cross-track data dependence. Since the rate-5/6 2D modulation code greatly improves the reliability of the middle-track, there is a bit-error rate gap between middle-track and sidetracks. Therefore, we propose the different track width writing technique to optimize the reliability of all three data tracks. In addition, we also evaluate the TDMR system performance using an user areal density capability (UADC) as a main key parameter. Here, an areal density capability (ADC) can be measured by finding the bit-error rate of the system with sweeping track and linear densities. The UADC is then obtained by removing redundancy from the ADC. Simulation results show that a system with our proposed techniques gains the UADC of about 4.66% over the conventional TDMR systems.

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