IEICE Transactions on Electronics
Online ISSN : 1745-1353
Print ISSN : 0916-8524
Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology
Design and Calibration of a Small-Footprint, Low-Frequency, and Low-Power Gate Leakage Timer Using Differential Leakage Technique
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2019 Volume E102.C Issue 4 Pages 269-275


This study proposes a design and calibration method for a small-footprint, low-frequency, and low-power gate leakage timer using a differential leakage technique for IoT applications. The proposed gate leakage timer is different from conventional ones because it is composed of two leakage sources and exploits differential leakage current for the charging capacitor. This solution alleviates the inherent trade-off between small-footprint and low-frequency in the conventional gate leakage timer. Furthermore, a calibration method to suppress variations of the output frequency is proposed in this paper. To verify the effectiveness of the proposed gate leakage timer, a test chip was fabricated using 55-nm-DDC-CMOS technology. The test chip successfully demonstrates the highest figure of merit (FoM) of the product of the capacitor area (0.072µm2) and output frequency (0.11Hz), which corresponds to an improvement by a factor of 2,121 compared to the conventional one. It also demonstrates the operation with 4.5pW power consumption. The total footprint can be reduced to be 28µm2, which enables low-cost and low-power IoT edges. The scaling scenario shows that the proposed technique is conducive to technology scaling.

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© 2019 The Institute of Electronics, Information and Communication Engineers
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