Bit-Parallel Systolic Architecture for AB and AB² Multiplications over GF(2^m)

抄録

In this paper, we present a scheme to compute either AB or AB² multiplications over GF(2^m) and propose a bit-parallel systolic architecture based on the proposed algorithm. The AB multiplication algorithm is derived in the same form as the formula of AB² multiplication algorithm, and an architecture that can perform AB multiplication by adding very little extra hardware to AB² multiplier is designed. Therefore, the proposed architecture can be effectively applied to hardware constrained applications that cannot deploy AB² multiplier and AB multiplier separately.