Ka-Band Stacked-FET Power Amplifier IC with Adaptively Controlled Gate Capacitor and Two-Step Adaptive Bias Circuit in 45-nm SOI CMOS

抄録

This paper presents a Ka-band high-efficiency power amplifier (PA) with a novel adaptively controlled gate capacitor circuit and a two-step adaptive bias circuit for 5th generation (5G) mobile terminal applications fabricated using a 45-nm silicon on insulator (SOI) CMOS process. The PA adopts a stacked FET structure to increase the output power because of the low breakdown voltage issue of scaled MOSFETs. The novel adaptive gate capacitor circuit properly controls the RF swing for each stacked FET to achieve high efficiency in the several-dB back-off region. Further, the novel two-step adaptive bias circuit effectively controls the gate voltage for each stacked FET for high linearity and high back-off efficiency. At a supply voltage of 4 V, the fabricated PA has exhibited a saturated output power of 20.0 dBm, a peak power added efficiency (PAE) of 42.7%, a 3dB back-off efficiency of 32.7%, a 6dB back-off efficiency of 22.7%, and a gain of 15.6 dB. The effective PA area was 0.82 mm by 0.74 mm.