Hardware oriented security and trust of semiconductor integrated circuit (IC) chips have been highly demanded. This paper outlines the requirements and recent developments in circuits and packaging systems of IC chips for security applications, with the particular emphasis on protections against physical implementation attacks. Power side channels are of undesired presence to crypto circuits once a crypto algorithm is implemented in Silicon, over power delivery networks (PDNs) on the frontside of a chip or even through the backside of a Si substrate, in the form of power voltage variation and electromagnetic wave emanation. Preventive measures have been exploited with circuit design and packaging technologies, and partly demonstrated with Si test vehicles.

This paper proposes a layer-wise tunable retraining method for edge FeFET Computation-in-Memory (CiM) to compensate the accuracy degradation of neural network (NN) by FeFET device errors. The proposed retraining can tune the number of layers to be retrained to reduce inference accuracy degradation by errors that occur after retraining. Weights of the original NN model, accurately trained in cloud data center, are written into edge FeFET CiM. The written weights are changed by FeFET device errors in the field. By partially retraining the written NN model, the proposed method combines the error-affected layers of NN model with the retrained layers. The inference accuracy is thus recovered. After retraining, the retrained layers are re-written to CiM and affected by device errors again. In the evaluation, at first, the recovery capability of NN model by partial retraining is analyzed. Then the inference accuracy after re-writing is evaluated. Recovery capability is evaluated with non-volatile memory (NVM) typical errors: normal distribution, uniform shift, and bit-inversion. For all types of errors, more than 50% of the degraded percentage of inference accuracy is recovered by retraining only the final fully-connected (FC) layer of Resnet-32. To simulate FeFET Local-Multiply and Global-accumulate (LM-GA) CiM, recovery capability is also evaluated with FeFET errors modeled based on FeFET measurements. Retraining only FC layer achieves recovery rate of up to 53%, 66%, and 72% for FeFET write variation, read-disturb, and data-retention, respectively. In addition, just adding two more retraining layers improves recovery rate by 20-30%. In order to tune the number of retraining layers, inference accuracy after re-writing is evaluated by simulating the errors that occur after retraining. When NVM typical errors are injected, it is optimal to retrain FC layer and 3-6 convolution layers of Resnet-32. The optimal number of layers can be increased or decreased depending on the balance between the size of errors before retraining and errors after retraining.

It is very important to design an embedded real-time system as a fault-tolerant system to ensure dependability. In particular, when a power failure occurs, restart processing after power restoration is required in a real-time system using a conventional processor. Even if power is restored quickly, the restart process takes a long time and causes deadline misses. In order to design a fault-tolerant real-time system, it is necessary to have a processor that can resume operation in a short time immediately after power is restored, even if a power failure occurs at any time. Since current embedded real-time systems are required to execute many tasks, high schedulability for high throughput is also important. This paper proposes a non-stop microprocessor architecture to achieve a fault-tolerant real-time system. The non-stop microprocessor is designed so as to resume normal operation even if a power failure occurs at any time, to achieve little performance degradation for high schedulability even if checkpoint creations and restorations are performed many times, to control flexibly non-volatile devices through software configuration, and to ensure data consistency no matter when a checkpoint restoration is performed. The evaluation shows that the non-stop microprocessor can restore a checkpoint within 5µsec and almost hide the overhead of checkpoint creations. The non-stop microprocessor with such capabilities will be an essential component of a fault-tolerant real-time system with high schedulability.

This paper presents a Ka-band high-efficiency power amplifier (PA) with a novel adaptively controlled gate capacitor circuit and a two-step adaptive bias circuit for 5th generation (5G) mobile terminal applications fabricated using a 45-nm silicon on insulator (SOI) CMOS process. The PA adopts a stacked FET structure to increase the output power because of the low breakdown voltage issue of scaled MOSFETs. The novel adaptive gate capacitor circuit properly controls the RF swing for each stacked FET to achieve high efficiency in the several-dB back-off region. Further, the novel two-step adaptive bias circuit effectively controls the gate voltage for each stacked FET for high linearity and high back-off efficiency. At a supply voltage of 4 V, the fabricated PA has exhibited a saturated output power of 20.0 dBm, a peak power added efficiency (PAE) of 42.7%, a 3dB back-off efficiency of 32.7%, a 6dB back-off efficiency of 22.7%, and a gain of 15.6 dB. The effective PA area was 0.82 mm by 0.74 mm.

This paper describes an in-depth analysis of crosstalk in a high-bandwidth 3D-stacked memory using a multi-hop inductive coupling interface and proposes two countermeasures. This work analyzes the crosstalk among seven stacked chips using a 3D electromagnetic (EM) simulator. The detailed analysis reveals two main crosstalk sources: concentric coils and adjacent coils. To suppress these crosstalks, this paper proposes two corresponding countermeasures: shorted coils and 8-shaped coils. The combination of these coils improves area efficiency by a factor of 4 in simulation. The proposed methods enable an area-efficient inductive coupling interface for high-bandwidth stacked memory.

Series-connection of resonant-tunneling diodes (RTDs) has been considered to be efficient in upgrading the output power when it is introduced to oscillator architecture. This work is for clarifying the same architecture also contributes to increasing oscillation frequency because the device parasitic capacitance is reduced M times for M series-connected RTD oscillator. Although this mechanism is expected to be universal, we restrict the discussion to the recently proposed multiphase oscillator utilizing an RTD oscillator lattice loop. After explaining the operation principle, we evaluate how the oscillation frequency depends on the number of series-connected RTDs through full-wave calculations. In addition, the essential dynamics were validated experimentally in breadboarded multiphase oscillators using Esaki diodes in place of RTDs.

We propose a radio-over-fiber (RoF) system with 1-bit outphasing modulation. The proposed RoF system does not require a power-hungry digital-to-analog converter in access points and relaxes the operation speed of optical transceivers to reduce device cost. We introduce two configurations to enable 1-bit outphasing modulation in our system; mixed-signal and all-digital configurations. In the mixed-signal configuration, the effects of harmonics and phase/amplitude mismatch on the adjacent channel leakage ratio (ACLR) were analyzed through simulation, and wideband transmission with a signal bandwidth of 400 MHz was experimentally verified, complying with the 3^rd Generation Partnership Project (3GPP) standard for millimeter-wave band. Moreover, wide-band transmission with a signal bandwidth of 1 GHz was also experimentally verified for beyond-5G and 6G. The all-digital configuration can be implemented in a standard digital design flow. This configuration was also verified to comply with the 3GPP standard by properly selecting the intermediate and sampling frequencies to mitigate the effects of folded harmonics and quantization noise. Finally, the proposed RoF system with both configurations has been shown to have a higher bandwidth efficiency compared with other systems complying with the 3GPP standard for the ACLR. Therefore, the proposed RoF system provides a cost-effective in-building wireless solution for 5G and 6G mobile network systems.

This paper presents a hippocampal cognitive prosthesis chip designed for restoring the ability to form new long-term memories due to hippocampal system damage. The system-on-chip (SOC) consists of a 16-channel micro-power low-noise amplifier (LNA), high-pass filters, analog-digital converters (ADCs), a 16-channel spike-sorter, a generalized Laguerre-Volterra model multi-input, multi-output (GLVM-MIMO) hippocampal processor, an 8-channel neural stimulator and peripheral circuits. The proposed LNA achieved a voltage gain of 50dB, input-referred noise of 3.95µV_rms, and noise efficiency factor (NEF) of 3.45 with the power consumption of 3.3µW. High-pass filters with a 300-Hz bandwidth are used to filter out the unwanted local field potential (LFP). 4 12-bit successive approximation register (SAR) ADCs with a signal-to-noise-and-distortion ratio (SNDR) of 63.37dB are designed for the digitization of the neural signals. A 16-channel spike-sorter has been integrated in the chip enabling a detection accuracy of 98.3% and a classification accuracy of 93.4% with power consumption of 19µW/ch. The MIMO hippocampal model processor predict output spatio-temporal patterns in CA1 according to the recorded input spatio-temporal patterns in CA3. The neural stimulator performs bipolar, symmetrical charge-balanced stimulation with a maximum current of 310µA, triggered by the processor output. The chip has been fabricated in 40nm standard CMOS technology, occupying a silicon area of 3mm².

This study proposes a low-complexity permittivity estimation for ground penetrating radar applications based on a contrast source inversion (CSI) approach, assuming multilayered ground media. The homogeneity assumption for each background layer is used to address the ill-posed condition while maintaining accuracy for permittivity reconstruction, significantly reducing the number of unknowns. Using an appropriate initial guess for each layer, the post-CSI approach also provides the dielectric profile of a buried object. The finite difference time domain numerical tests show that the proposed approach significantly enhances reconstruction accuracy for buried objects compared with the traditional CSI approach.