Back- and Front-Interface Trap Densities Evaluation and Stress Effect of Poly-Si TFT

Abstract

The polycrystalline silicon (poly-Si) TFT has two insulator interfaces between the polycrystalline silicon and front and back insulators. These interfaces have trap states, which affect the characteristics of poly-Si TFT. In the silicon-on-insulator (SOI) technology area, using the dual-gated, fully-depleted SOI MOSFET under the depleted back-channel condition, the back-interface trap density can be calculated through the front-channel threshold voltage and film thicknesses. The front-interface trap density is also evaluated changing the roles of both gates. This evaluation method for front- and back-interface trap densities is called the threshold-voltage method. To apply this threshold-voltage method to the “medium-thickness” poly-Si TFT, of which the channel is not fully depleted in normal single gate bias operation, the biases for both front and back gates are controlled to realize full depletion. Under the fully-depleted condition, the front- or back-threshold voltage of poly-Si TFT is carefully extracted by the second-derivative method changing back- and front-gate biases. We evaluated the front- and back-interface trap densities not only for normal operation but also under stress. To evaluate the bias and temperature stress effect, we used two types of samples, which are made by different processes. The evaluated front- and back-interface trap densities for both samples in initial state are around 5×10¹¹ to 1.3×10¹²cm^-2eV^-1, which are almost the same as the reported values. Applying bias and temperature stress shows the variation of these interface-trap densities. Samples with large shifts of the front-channel threshold voltage show large trap density variation. On the other hand, samples with small threshold voltage shifts show small trap density variation. The variation of the back-interface trap density during the stress application showed a correlation to the front-channel threshold voltage shift.