IEICE Transactions on Electronics
Online ISSN : 1745-1353
Print ISSN : 0916-8524
Regular Section
A Novel Fast-Lock-in Digitally Controlled Phase-Locked Loop
Xin CHENJun YANGLong-xing SHI
著者情報
ジャーナル 認証あり

2008 年 E91.C 巻 12 号 p. 1971-1975

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抄録
A novel fast lock-in digitally controlled phase-locked loop (DCPLL) is proposed in this letter. This DCPLL adopts a novel frequency search algorithm to reduce the lock-in time. Furthermore, to reduce the power consumption, the frequency divider is reused as a frequency detector during the frequency acquisition, and reused as a time-to-digital converter module during the phase acquisition. To verify the proposed algorithm and architecture, a DCPLL design is implemented by SMIC 0.18µm 1P6M CMOS technology. The Spice simulation results show that the DCPLL can achieve frequency acquisition in 3 reference cycles and complete phase acquisition in 11 reference cycles when locking to 200MHz. The corresponding power consumption of DCPLL is 3.71mW.
著者関連情報
© 2008 The Institute of Electronics, Information and Communication Engineers
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