IEICE Transactions on Electronics
Online ISSN : 1745-1353
Print ISSN : 0916-8524
Special Section on Advanced Technologies in Digital LSIs and Memories
Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling
Masanori HARIYAMANaoto YOKOYAMAMichitaka KAMEYAMA
著者情報
キーワード: stereo vision, scheduling, allocation
ジャーナル 認証あり

2008 年 E91.C 巻 4 号 p. 479-486

詳細
抄録
This paper presents a processor architecture for high-speed and reliable tinocular stereo matching based on adaptive window-size control of SAD (Sum of Absolute Differences) computation. To reduce its computational complexity, SADs are computed using images divided into non-overlapping regions, and the matching result is iteratively refined by reducing a window size. Window-parallel-and-pixel-parallel architecture is also proposed to achieve to fully exploit the potential parallelism of the algorithm. The architecture also reduces the complexity of an interconnection network between memory and functional units based on regularity of reference pixels. The stereo matching processor is designed in a 0.18μm CMOS technology. The processing time is 83.2μs@100MHz. By using optimal scheduling, the increases in area and processing time is only 5% and 3% respectively compared to binocular stereo vision although the computational amount is double.
著者関連情報
© 2008 The Institute of Electronics, Information and Communication Engineers
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