Concise Modeling of Transistor Variations in an LSI Chip and Its Application to SRAM Cell Sensitivity Analysis

Abstract

Random variations in I_d-V_g characteristics of MOS transistors in an LSI chip are shown to be concisely characterized by using only 3 transistor parameters (V_th, β₀, υ_SAT) in the MOS level 3 SPICE model. Statistical analyses of the transistor parameters show that not only the threshold voltage variation, ΔV_th, but also the current factor variation, Δβ₀, independently induces I_d-variation, and that Δβ₀ is negatively correlated with the saturation velocity variation, Δυ_SAT. Using these results, we have proposed a simple method that effectively takes the correlation between parameters into consideration when creating statistical model parameters for designing a circuit. Furthermore, we have proposed a sensitivity analysis methodology for estimating the process window of SRAM cell operation taking transistor variability into account. By applying the concise statistical model parameters to the sensitivity analysis, we are able to obtain valid process windows without the large volume of data-processing and long turnaround time associated with the Monte Carlo simulation. The processs window was limited not only by ΔV_th, but also by Δβ₀ which enhanced the failure region in the process window by 20%.