IEICE Transactions on Electronics
Online ISSN : 1745-1353
Print ISSN : 0916-8524
Special Section on Fundamentals and Applications of Advanced Semiconductor Devices
Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)
Seongjae CHOHan PARKJung Hoon LEEJang-Gn YUNDoo-Hyun KIMJong Duk LEEHyungcheol SHINByung-Gook PARK
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2008 Volume E91.C Issue 5 Pages 731-735


Efforts have been devoted to maximizing memory array densities. However, as the devices are scaled down in dimension and getting closer to each other, electrical interference phenomena among devices become more prominent. Various features of 3-D memory devices are proposed for the enhancement of memory array density. In this study, we mention 3-D NAND flash memory device having pillar structure as the representative, and investigate the paired cell interference (PCI) which inevitably occurs in the read operation for 3-D memory devices in this feature. Furthermore, criteria for setting up the read operation bias schemes are also examined in existence with PCI.

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© 2008 The Institute of Electronics, Information and Communication Engineers
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