Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme

抄録

In this paper, characteristics of the 2-bit recessed channel memory with lifted-charge trapping nodes are investigated. The length between the charge trapping nodes through channel, which is defined as the effective memory node length (M_eff), is extended by lifting up them. The dependence of V_TH window and short channel effect (SCE) on the recessed depth is analyzed. Improvement of short channel effect is achieved because the recessed channel structure increases the effective channel length (L_eff). Moreover, this device shows highly scalable memory characteristics without suffering from the bottom-side effect (BSE).