This paper reports the new gate and recess structure design of millimeter-wave, high power pHEMTs, which highly improves humidity resistance and reliability. By using tantalum nitride as the refractory gate metal and a silicon nitride layer prepared by a catalytic chemical vapor deposition technique for passivation of this transistor, strong moisture resistance was obtained without degradation of the device characteristics. Moreover, we have designed a stepped recess structure to increase the on-state breakdown voltage without degradation of the power density of the millimeter-wave pHEMT, according to the analysis based on the new nonlinear drain resistance model. Consequently, the developed pHEMT has shown strong humidity resistance with no degradation of the DC characteristics even after 1000 hours storage at 400K and 85% humidity, and the high on-state breakdown voltage of over 30V while keeping the high power density of 0.65W/mm in the Ka band. In addition, the proposed nonlinear drain resistance model effectively explains this power performance.

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In this study, we have performed both the channel modification of the conventional MHEMT (Metamorphic High Electron Mobility Transistor) and the variation of gate recess width to improve the breakdown and RF characteristics. The modified channel consists of the In_xGa_1-xAs and the InP layers. Since InP has lower impact ionization coefficient than In_0.53Ga_0.47As, we have adopted the InP-composite channel in the modified MHEMT. Also, the gate recess width is both functions of breakdown and RF characteristic of a HEMT structure. Therefore, we have studied the breakdown and RF characteristic for various gate recess widths in MHEMT. We have compared breakdown characteristic of the InP-composite channel with that of conventional MHEMT. It is shown that on and off state breakdown voltages of the InP-composite channel MHEMT were increased by about 20 and 27%, respectively, compared with the conventional structure. Also, breakdown voltage of the InP-composite channel MHEMT was increased with increasing gate recess width. The f_T was increased with decreasing the gate recess width, whereas f_max was increased with increasing the gate recess width. Also, we extracted small-signal parameters. It was shown that G_d of the InP-composite channel MHEMT is decreased about by 30% compared with the conventional MHEMT. Therefore, the suppression of the impact ionization in the InP-composite channel increases the breakdown voltage and decreases the output conductance.

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HEMT comparators for ultrahigh-speed A/D converters have been investigated. In particular, the transition times of the D-latch used in the comparator have been analyzed by assuming a 0.1-μm HEMT technology. It is found that for small input signals (<0.1V), the transition time from the track to latch phase dominates the comparator operation speed. As the input signal increases, this time decreases due to the positive feedback in the latch, and the comparator speed is limited by the transition time from the latch to track phase. The transition times of 20ps have been estimated for the present comparator.

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We studied planar graded-gap injector GaAs Gunn diodes designed for operation at 94GHz. Two types of planar Gunn diodes were designed and fabricated. In the first diode, a cathode was situated inside a circular anode with a diameter of 190μm. The distance between the anode and cathode varied from 60μm to 68μm depending on the cathode size. Also, we designed a structure with a constant distance between the anode and cathode of 10μm. In the second diode, the anode was situated inside the cathode for the flip-chip mounting on the oscillator circuits. The fabrication of the Gunn diode was based on ohmic contact metallization, mesa etching, and air-bridge and overlay metallization. DC measurements were carried out, and the nature of the negative differential resistance, the operating voltage, and the peak current in the graded-gap injector GaAs Gunn diodes are discussed for different device structures. It is shown that the structure with the shorter distance between the cathode and anode has a higher peak current, higher breakdown voltage, and lower threshold voltage than those of the structure with the larger distance between the cathode and anode.

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Device characteristics of In_0.5Ga_0.5As/GaAs quantum dot infrared detector (QDIP) have been enhanced with hydrogen plasma treatment. After the hydrogen (H) plasma treatment, the dark currents were noticeably decreased and photoluminescence (PL) intensity was increased by H-passivation of interfacial traps between quantum dots and GaAs and of non-radiative defect centers caused during QD growths. Photo response, which could not be observed in as-grown QDIP due to large dark currents which obscured the photocurrent signal, was measured successfully after H-treatment due to H-passivation.

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PIN diodes for digital X-ray detection as a single photon counting sensor were fabricated on a floating-zone (FZ) n-type (111), high resistivity (5-10 kΩcm) silicon substrates (500μm thickness). Its electrical properties such as the leakage current and the breakdown voltage were characterized. The size of pixels was 100μm×100μm. The p⁺ guard-ring was formed around the active area to reduce the leakage current. After the p⁺ active area and guard-ring were fabricated by the ion-implantation, the extrinsic-gettering on the wafer backside was performed to reduce the leakage current by n⁺ ion-implantation. PECVD oxide was deposited as an IMD layer on front side and then, metal lines were formed on both sides of wafers. The leakage current of detectors was significantly reduced with a guard-ring when compared with that without a guard ring. The leakage current showed the strong dependency on the gap distance between the active area and the guard ring. It was possible to achieve the leakage current lower than 0.2nA/cm².

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Effects of Fe/Si ratio and growth temperature were investigated in order to realize high quality Fe₃Si/Ge structures. It was found that very small Xmin values (2-3%) were achieved in a wide temperature range of 60-200°C under the stoichiometric condition. From TEM observation, it was rvealed that the Fe₃Si/Ge structures with atomically flat interfaces were realized. In addition, thermal stability of the Fe₃Si/Ge structures was guaranteed up to 400°C. These results suggested that growth at a low temperature (<200°C) under the stoichiometric condition was essential to obtain high quality Fe₃Si/Ge structures with sharp interfaces.

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Multiply-stacked structures of Si quantum dots (Si-QDs) in gate oxide are attracting much attention because of their potential importance to improve retention characteristics in a high density charge storage. In this work, we have fabricated 6-fold stacked Si-QDs with 2nm-thick SiO₂ interlayers, whose areal dot density and average dot size were 5.7×10¹¹cm^-2 in each dot layer and -5nm in height, and studied progress on electron distribution in 6-fold stacked Si-QDs with 2nm-thick SiO₂ interlayers from the measurements of temporal changes in the surface potential after electron charging and discharging locally at room temperature using an AFM/Kelvin probe technique in clean room air. First, by scanning an area of 2×2μm² with the AFM tip biased at +3V with respect to the substrate in a tapping mode, the area was negatively charged due to electron injection from the substrate to the dot through the bottom tunnel oxide and subsequently, the central part of 100×100nm² in the pre-charged area was scanned with the tip biased at -3V to emit the electrons from the Si-QDs to the substrate. As a result, the negative charging level was markedly reduced in the central part in comparison to its peripheral region. And then, the surface potential of the negatively-charged peripheral region was decay monotonously with time as a result of progressive electron tunneling to the substrate. In contrast to this, the temporal change in the surface potential of the central part shows that the electron charging proceeds with time until the surface potential becomes almost the same as that in the peripheral region. This result can be interpreted in terms of lateral spreading of electrons stored in the Si-QDs layer due to the potential difference between the central part and its peripheral region more negatively charged.

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The stress effect of SiGe p-type metal oxide semiconductor field effect transistors (MOSFETs) has been investigated to compare their properties associated with the Si_0.88Ge_0.12/Si epi channels grown on the Si bulk and partially depleted silicon on insulator (PD SOI) substrates. The stress-induced changes in the subthreshold slope and the drain induced barrier lowering were observed small in the SiGe PD SOI in comparison to in the SiGe bulk. Likewise the threshold voltage shift monitored as a function of hot carrier stress time presented excellent stability than in the SiGe PD SOI. Therefore, simply in terms of do properties, the SiGe PD SOI looks more immune from electrical stresses than the SiGe bulk. However, the 1/f noise properties revealed that the hot carrier stress could introduce lots of generation-recombination noise sources in the SiGe PD SOI. The quality control of oxide-silicon in SOI structures is essential to minimize a possible surge of 1/f noise level due to the hot carrier injection. In order to improve dc and rf performance simultaneously, it is very important to grow the SiGe channels on high quality SOI substrates.

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This paper presents an asynchronous design technique, an enabler for the emerging technology of flexible microelectronics that feature low-temperature processed polysilicon (LTPS) thin-film transistors (TFT) and surface-free technology by laser annealing/ablation (SUFTLA^®). The first design instance chosen is an 8-bit microprocessor. LTPS TFTs are good for realizing displays having integrated VLSI circuit at lower costs. However, LTPS TFTs have drawbacks, including substantial deviations in characteristics and the self-heating phenomenon. To solve these problems, the authors adopted the asynchronous circuit design technique and developed an asynchronous design language called Verilog+, which is based on a subset of Verilog HDL^® and includes minimal primitives used for describing the communications between modules, and the dedicated tools including a translator called xlator and a synthesizer called ctrlsyn. The flexible 8-bit microprocessor stably operates at 500kHz, drawing 180μA from a 5V power source. The microprocessor's electromagnetic emissions are 21dB less than those of the synchronous counterpart.

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Efforts have been devoted to maximizing memory array densities. However, as the devices are scaled down in dimension and getting closer to each other, electrical interference phenomena among devices become more prominent. Various features of 3-D memory devices are proposed for the enhancement of memory array density. In this study, we mention 3-D NAND flash memory device having pillar structure as the representative, and investigate the paired cell interference (PCI) which inevitably occurs in the read operation for 3-D memory devices in this feature. Furthermore, criteria for setting up the read operation bias schemes are also examined in existence with PCI.

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A new SONOS flash memory device with recess channel and side-gate was proposed and designed in terms of recess depth, doping profile, and side-gate length for sub-40nm flash memory technology. The key features of the devices were characterized through 3-dimensional device simulation. This cell structure can store 2 or more bits of data in a cell when it is applied to NOR flash memory. It was shown that channel doping profile is very important depending on NOR or NAND applications. In NOR flash memory application, the localized channel doping under the source/drain junction is very important in designing threshold voltage (V_th) and suppression of drain induced barrier lowering (DIBL). In our work, this cell structure is studied not only for NAND flash memory application but also for NOR flash application. The device design was performed in terms of electrical characteristics (V_th, DIBL and SS) by considering device structure and doping profile of the cell.

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In this paper, characteristics of the 2-bit recessed channel memory with lifted-charge trapping nodes are investigated. The length between the charge trapping nodes through channel, which is defined as the effective memory node length (M_eff), is extended by lifting up them. The dependence of V_TH window and short channel effect (SCE) on the recessed depth is analyzed. Improvement of short channel effect is achieved because the recessed channel structure increases the effective channel length (L_eff). Moreover, this device shows highly scalable memory characteristics without suffering from the bottom-side effect (BSE).

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We fabricated the floating gate for silicon-on-insulator nonvolatile memory devices with In₂O₃ nano-particles embedded in polyimide insulator. Self-assembled In₂O₃ nano-particles were created by chemical reaction between the biphenyl dianhydride-p-phenylenediamine polymer precursor and indium films. The particles size and density of In₂O₃ nano-particles were 7nm and 6×10¹¹cm^-2, respectively. The current-voltage and retention time of fabricated device were characterized by using semiconductor parameter analyzer. A significant threshold voltage shift of fabricated nano-floating gate memory devices obtained, because of the charging effects of In₂O₃ nano-particles. And a memory window measured about 1V at initial status.

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A novel design for temperature-compensated complementary metal-oxide semiconductor (CMOS) voltage reference sources by using the 1st order voltage reference taking into account the electrical property of the conventional current generator was proposed to minimize a temperature coefficient. A temperature coefficient of the proposed voltage reference source was estimated by using the current generator, which operated at smaller or larger temperature in comparison with the optimized operating temperature. The temperature coefficient at temperature range between -40°C and 125°C, obtained from the simulated data by using hynix 0.35μm CMOS technology, was 3.33ppm/°C. The simulated results indicate that the proposed temperature-compensated CMOS voltage reference sources by using the 1st order voltage reference taking into account the electrical properties of the conventional current generator can be used to decrease the temperature coefficient.

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A scalable DC model of lateral double diffused MOSFETs (LDMOSFETs) is presented in this paper. This model is based on physical analysis considering device geometry, carrier distributions, mobility degradation effect, and the effect of impact ionization. In this model, we divide the LDMOSFET into two regions to obtain the physical conduction model: one is channel region and the other is drift region. The channel region model is based on the BSIM3v3 model and the drift region employs voltage dependent resistance model considering the length of depleted region in the drift region. The modeling results are compared with measured I-V characteristics and the results show good agreements with the maximum error of 10% compared to the measured results of devices.

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This study describes the dependence of the surface electric field to the junction depth of source/drain-extension, and the suppression of gate induced drain leakage (GIDL) in fully depleted shallow junction gate-overlapped source/drain-extension (SDE). The GIDL can be reduced by reducing shallow junction depth of drain-extension. Total space charges are a function of junction depth in fully depleted shallow junction drain-extension, and the surface potential is proportional to these charges. Because the GIDL is proportional to surface potential, GIDL is the function of junction depth in fully depleted shallow junction drain-extension. Therefore, the GIDL is suppressed in a fully depleted shallow junction drain-extension by reducing surface potential. Negative substrate bias and halo doping could suppress the GIDL, too. The GIDL characteristic under negative substrate bias is contrary to other GIDL models.

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This paper presents the selective epitaxial growth (SEG) properties of reduced pressure chemical vapor deposition (RPCVD) at low temperatures (LT) of 675-725°C with high aspect ratio mask of dielectric films. The SEG process could be explained in conjunction with the loading effect, the mask pattern shape/size, and the process parameters of RPCVD. The growth rates showed a large non-uniformity up to 40% depending upon the pattern size of the dielectric mask films, but as the SEG film becomes thicker, the growth rate difference converged on -15% between the narrow 2-μm and the wide 100-μm patterns. The evolution of SEG was controlled dominantly by the surface migration control at the initial stage, and converted to the surface topology control. The design of pattern size and distribution with dummy patterns must be useful to accomplish the reliable and uniform LT-SEG.

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In this study, the microwave dielectric properties of the Mg₄Ta₂O₉ and Mg₅Ta₄O₁₅ ceramics with composition ratio and sintering temperature were investigated and the dielectric resonators with these ceramics were simulated. TiO₂ was doped in the Mg₄Ta₂O₉ ceramics for improvement of temperature property. The (1-x)Mg₄Ta₂O₉-xTiO₂ and Mg₅Ta₄O₁₅ ceramics were prepared by solid-state reaction method. According to the X-ray diffraction data, the (1-x)Mg₄Ta₂O₉-xTiO₂ ceramics had main phase of the Mg₄Ta₂O₉ and MgTi₂O₅ peaks were appeared by additions of TiO₂. In the Mg₅Ta₄O₁₅ ceramics, the Mg₄Ta₂O₉ and MgTa₂O₆ phase were coexisted and Mg₅Ta₄O₁₅ phase was appeared with increments of sintering temperature. Microwave dielectric properties of (1-x)Mg₄Ta₂O₉-xTiO₂ ceramics were affected by MgTi₂O₅ and TiO₂ phase. The quality factor had a little decrement compared to pure Mg₄Ta₂O₉, but there was excellent improvement in TCRF by addition of TiO₂. Densifications of the Mg₄Ta₂O₉ and MgTa₂O₆ and existence of the Mg₅Ta₄O₁₅ phase had influence on the microwave dielectric properties of the Mg₅Ta₄O₁₅ ceramics. Dielectric constant, quality factor and TCRF of the (1-x)Mg₄Ta₂O₉-xTiO₂ and Mg₅Ta₄O₁₅ ceramics sintered at 1450°C were 11.56-22.5, 24980-186410GHz, -36.02-+19.72ppm/°C and 8.2, 89473GHz, -10.91ppm/°C, respectively. ADS was used for simulation of DR. The simulated DR with the 0.5Mg₄Ta₂O₉-0.5TiO₂ and Mg₅Ta₄O₁₅ ceramics had the S₂₁ of -35.034dB at 11.97GHz and -28.493 dB at 10.50GHz, respectively.

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As the gate area decreases to the order of a square micron, individual trapping events can be detected as fluctuations between discrete levels of the drain current, known as random telegraph signal (RTS) noise. Many circuit application areas such as CMOS Image sensor and flash memory are already suffering from RTS noise. Especially, in case of flash memory, FN stress causes threshold voltage shift problems due to generation of additional oxide traps, which degrades circuit performance. In this paper, we investigated how FN stress effects on RTS noise behavior in MOSFET and monitored it in both the time domain and frequency domain.

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This paper presents a new quarter-wavelength microstrip coupler compensated with a periodic sequence of floating metallic strips in the slots on the inner edges. After describing the characteristics of the coupled-line, as an example, a 15-dB coupler is designed and a high directivity of 30dB or more in theory is obtained over a full band of a single-section coupler. Next, couplers with various coupling factors are designed, and the usefulness for very loose coupling is demonstrated. Furthermore, a three-section coupler is designed to show the effectiveness in a wide frequency range. The validity of the design concept and procedure is confirmed by electromagnetic simulations and experiments.

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Two variable gain amplifiers (VGAs) that adopt new approximated exponential equations are proposed in this paper. The dB-linear range of the proposed VGAs is extended more than what the approximated exponential equations predict by a bias circuit technique that adopts negative feedback. The proposed VGAs feature wide gain variation, low-power, high linearity, wide control signal range, and small chip size. One of the proposed VGAs is fabricated in 0.18μm CMOS technology and measurements show a gain variation of 83dB (-36-47dB) with a gain error of less than ±2dB, and P1dB/IIP3 from -55/8 to -20/20.5dBm, while consuming an average current of 3.4mA from a 1.8V supply; the chip occupies 0.4mm². The other VGA is simulated in 0.18μm CMOS technology and simulations show a gain variation of 91dB (-41-50dB), and P1dB/IIP3 from -50/-25 to -33/0dBm, while consuming an average current of 1.5mA from a 1.8V supply.

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In this paper, we present a multiple capture approach to reducing the peak power as well as average power consumption during testing. The basic idea behind is to divide a scan chain into two sub-scan chains, and only one sub-scan chain will be enabled at a time during the scan shift or capture operations. We develop a pattern insertion technique to efficiently deal with the capture violation problem during the capture cycle. In order to alleviate the timing cost due to the insertion of redundant patterns, a scan chain partitioning method incorporated with test pattern reordering is developed to reduce the testing time. Experimental results for large ISCAS'89 benchmark circuits show that the proposed approach can efficiently reduce peak and average power with little timing overhead.

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An all CMOS variable gain amplifier (VGA) which features wide dB-linear gain range per stage (45dB), low power consumption (1.32mW), small chip size (0.13mm²), and low supply voltage (1.2V) is described. The dB-linear range is extended by reducing the supply voltage of the conventional V-to-I converter. The two-stage VGA implemented in 0.18μm CMOS offers 90dB of gain variation, 3dB bandwidth of greater than 21MHz, and max/min input IP3 and P1 dB, respectively, of -5/-42 and -12/-50 dBm.

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For battery-powered electronic products, one way to extend battery life is to use a versatile step-up/step-down DC-DC converter. A new versatile step-up/step-down switched-capacitor-based converter structure is proposed, and its efficiency is analyzed. In the step-down case, the efficiency is the same as, or even better than the efficiency of linear regulators.

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