2008 年 E91.C 巻 9 号 p. 1525-1528
Two phase detectors (PD) are proposed to minimize the phase offset and deadzone when used in DLL or PLL. With the shortest symmetrical racing paths from both inputs, the binary PD achieves fast latch operation and theoretical elimination of the setup time. In contrast to the conventional PDs whose offsets are around 10ps with large sensitivity to sizing, the proposed binary PD shows an offset of less than 1ps with a reduction of 30-percent delay time. The proposed latch-type binary phase detection is also expanded to form a linear PD by the addition of a reset-generating circuit.
