This paper presents the processor architecture which provides much higher level dependability than the current ones. The features of it are: (1) fault tolerance and secure processing are integrated into a modern superscalar VLSI processor; (2) light-weight effective soft-error tolerant mechanisms are proposed and evaluated; (3) timing errors on random logic and registers are prevented by low-overhead mechanisms; (4) program behavior is hidden from the outer world by proposed address translation methods; (5) information leakage can be avoided by attaching policy tags for all data and monitoring them for each instruction execution; (6) injection attacks are avoided with much higher accuracy than the current systems, by providing tag trackings; (7) the overall structure of the dependable processor is proposed with a dependability manager which controls the detection of illegal conditions and recovers to the normal mode; and (8) an FPGA-based testbed system is developed where the system clock and the voltage are intentionally varied for experiment. The paper presents the fundamental scheme for the dependability, elemental technologies for dependability and the whole architecture of the ultra dependable processor. After showing them, the paper concludes with future works.

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The deep submicron semiconductor technologies will make the worst-case design impossible, since they can not provide design margins that it requires. We are investigating a typical-case design methodology, which we call the Constructive Timing Violation (CTV). This paper extends the CTV concept to collapse dependent instructions, resulting in performance improvement. Based on detailed simulations, we find the proposed mechanism effectively collapses dependent instructions.

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We propose a CMOS image sensor that realizes wide dynamic rangee imaging and nonlinear representation of I/O characteristics. The proposed image sensor controls the integration time for each pixel based on the brightness distribution of objects. The histogram at the end of the integration is estimated from the early intermediate photodiode values that are read out to an external circuit. Using the estimated histogram, the imaging parameters, which control the integration time pixel-by-pixel, are optimized in the external circuit. According to the imaging parameters, the intermediate photodiode value is compared with the threshold and reset to the starting value depending on the comparison result. These processes repeat several times. At the end of the integration, the photodiode value is reconstructed by using the imaging parameters. Then, wide dynamic range images with adapted I/O characteristics are obtained. We have fabricated a prototype with a size of 64×64 pixels using a 0.35-μm 2-poly 4-metal CMOS process. In this paper, we explain the principle of the proposed sensor and discuss the system architecture and its operation. The experimental results obtained using the prototype are also presented, and we verify its effectiveness.

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This paper presents an integration architecture of content addressable memory (CAM) and a massive-parallel memory-embedded SIMD matrix for constructing a versatile multimedia processor. The massive-parallel memory-embedded SIMD matrix has 2,048 2-bit processing elements, which are connected by a flexible switching network, and supports 2-bit 2,048-way bit-serial and word-parallel operations with a single command. The SIMD matrix architecture is verified to be a better way for processing the repeated arithmetic operation types in multimedia applications. The proposed architecture, reported in this paper, exploits in addition CAM technology and enables therefore fast pipelined table-lookup coding operations. Since both arithmetic and table-lookup operations execute extremely fast, the proposed novel architecture can realize consequently efficient and versatile multimedia data processing. Evaluation results of the proposed CAM-enhanced massive-parallel SIMD matrix processor for the example of the frequently used JPEG image-compression application show that the necessary clock cycle number can be reduced by 86% in comparison to a conventional mobile DSP architecture. The determined performances in Mpixel/mm² are factors 3.3 and 4.4 better than with a CAM-less massive-parallel memory-embedded SIMD matrix processor and a conventional mobile DSP, respectively.

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This paper presents a novel asynchronous architecture of Field-programmable gate arrays (FPGAs) to reduce the power consumption. In the dynamic power consumption of the conventional FPGAs, the power consumed by the switch blocks and clock distribution is dominant since FPGAs have complex switch blocks and the large number of registers for high programmability. To reduce the power consumption of switch blocks and clock distribution, asynchronous bit-serial architecture is proposed. To ensure the correct operation independent of data-path lengths, we use the level-encoded dual-rail encoding and propose its area-efficient implementation. The proposed field-programmable VLSI is implemented in a 90nm CMOS technology. The delay and the power consumption of the proposed FPVLSI are respectively 61% and 58% of those of 4-phase dual-rail encoding which is the most common encoding in delay insensitive encoding.

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Modern microprocessors achieve high application performance at the acceptable level of power dissipation. In terms of power to performance trade-off, the instruction window is particularly important. This is because enlarging the window size achieves high performance but naive scaling of the conventional instruction window can severely increase the complexity and power consumption. In this paper, we propose low-power instruction window techniques for contemporary microprocessors. First, the small reorder buffer (SROB) reduces power dissipation by deferred allocation and early release. The deferred allocation delays the SROB allocation of instructions until their all data dependencies are resolved. Then, the instructions are executed in program order and they are released faster from the SROB. This results in higher resource utilization and low power consumption. Second, we replace a conventional issue queue by a direct lookup table (DLT) with an efficient tag translation technique. The translation scheme resolves the instruction dependency, especially for the case of one producer to multiple consumers. The efficiency of the translation scheme stems from the fact that the vast majority of instruction dependency exists within a basic block. Experimental results show that our proposed design reduces the power consumption significantly for SPEC2000 benchmarks.

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A fine-grain reconfigurable VLSI for various applications including arithmetic operations is developed. In the fine-grain architecture, it is important to define a cell function which leads to high utilization of a logic block and reduction of a switch block. From the point of view, a universal-literal-based multiple-valued cell suitable for bit-serial reconfigurable computation is proposed. A series-gating differential-pair circuit is effectively employed for implementing a full-adder circuit of Sum and a universal literal circuit. Therefore, a simple logic block can be constructed using the circuit technology. Moreover, interconnection complexity can be reduced by utilizing multiple-valued signaling, where superposition of serial data bits and a start signal which indicates heading of one-word is introduced. Differential-pair circuits are also effectively employed for current-output replication, which leads to high-speed signaling to adjacent cells The evaluation is done based on 90nm CMOS design rule, and it is made clear that the area of the proposed cell can be reduced to 78% in comparison with that of the CMOS implementatiuon. Moreover, its area-time product becomes 92% while the delay time is increased by 18%.

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A transceiver macro for high-speed data transmission via cable in vehicles is proposed. The transceiver uses ac coupling and bidirectional interface topology for protecting LSIs against unexpected short of cable and harness/chassis and has a spread-spectrum-clocking (SSC) generator that reduces noise due to electromagnetic interference. A driver current control has been used for fast switching of data direction on accoupled interfaces. An adaptive bandwidth control has been used in a ΔΣ PLL to improve SCC significantly. A test chip has been fabricated and shows stable and bi-directional data communication with data rate of 162 to 972 Mbps through 20-m cable. Thanks to an optimum calibration of the SSC-PLL bandwidth, it reduces peak power at 33kHz by -23dB and provides 2% modulation at a data rate of 810Mbps.

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The novel low-power and low-EMI-noise current-mode data transceiver described here, which has a multilevel current driver in the transmitter (TX) and a low-input impedance I-V converter in the receiver (RX). No-feedback clock recovery in the RX is achieved by using multi-levels of a driving current from TX to specify a single bit boundary. The I-V converter suppresses voltage swing in the transmission line and generates a multi-level voltage signal according to the level of the submilliampere driving current it receives. Measurement shows a small voltage swing (≈20mV) with 150-μA and 450-μA drive currents at 625Mbps. The simple clock-recovery system and low driving current allow the transceiver to operate with a single 1.5-V power supply and use only 3.5mW at 625Mbps.

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This paper presents the near-field to far-field transformation for an outdoor radar cross section (RCS) range. Direct measurement of the large actual target requires quite a long measurement range. The near-field to far-field RCS transformation method achieves the reduction of measurement range. However the non-uniformity of the incident electric field distribution on the target causes some errors in RCS prediction. We propose a novel near-field to far-field RCS transformation method that can be applied to an outdoor RCS measurement. The non-uniformity of the incident electric field distribution is successfully resolved by introducing the correction term of the ground bounce. We investigate the validity of the proposed method by the simulation and measurement.

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Simulation and fabrication results on back-illuminated 4-channel photodiode (PD) array with a self-aligned micro ball lens are described. The channel pitch and diameter of each photosensitive area are 250μm and 40μm, respectively. Measured photocurrent is 1.92 times larger than that without a lens. Alignment tolerance between the single mode fiber (SMF) optical axis and the photodiode is improved from 21.2μm to 42.7μm. Moreover, the separation tolerance between the fiber and the lens is 210.5μm. These large tolerances agree with simulation results, demonstrating that the device configuration is suitable for receivers for multi-channel inter-connection. Frequency response and inter-channel cross talk are also discussed.

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This paper proposes a low-voltage high-speed sample-and-hold (S/H) structure with excellent power efficiency. Based on the switched-opamp technique, an inverse-flip-around architecture which maximizes the feedback factor is employed in the proposed S/H. A skew-insensitive double-sampling mechanism is presented to increase the throughput by a factor of two while eliminating the timing mismatch associated with double-sampling circuits. Furthermore, a dual-input dual-output opamp is proposed to incorporate double-sampling into the switched-opamp based S/H. This opamp also removes the memory effect in double-sampling circuitry and features fast turn-on time to improve the speed performance in switched-opamp circuits. Simulation results using a 0.13-μm CMOS process model demonstrates the proposed S/H circuit has a total-harmonic-distortion of -67.3dB up to 250MSample/s and a 0.8V_PP input range at 0.8V supply. The power consumption is 3.5mW and the figure-of-merit is only 7.4fJ/step.

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An analytical model of the static noise margin (SNM) for a 6T CMOS SRAM suitable for use in investigating the effect of random V_th variation is derived. A three-step approach using characteristic points of the half cell inverter's transfer curve is developed. Parameters of each transistor are handled individually so that their sensitivities are calculable. A new MOSFET model in the moderate inversion is proposed to maintain accuracy, even in the low V_DD condition. Correlation between the proposed model calculations and circuit simulations was verified using a 90nm CMOS LSTP device. Closely correlated dependency on parameters such as V_th, the W ratio, and V_DD were obtained. Maximum error measured in the V_DD range of 0.6-1.6V was 16mV (7% of typical SNM). Finally, guidelines to obtain large SNM are discussed in this paper.

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Programmable Metallization Cell (PMC) Random Access Memory is based on the electrochemical growth and removal of nanoscale metallic pathways in thin films of solid electrolytes. In this study, we investigate the nature of thin films formed by the photo doping of Cu into chalcogenide materials for use in programmable metallization cell devices. These devices rely on metal ion transport in the film so produced to create electrically programmable resistance states. The results imply that a Cu-rich phase separates owing to the reaction of Cu with free atoms from chalcogenide materials.

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Source-drain follower has been designed and implemented for monolithically integrated biosensor array. The circuit acts as a voltage follower, in which a sensing transistor is operated at fixed gatesource and gate-drain voltages. It operates at 10nW power dissipation. The wide-swing cascode configurations are investigated in constant and non-constant biasing methods. The constant biased cascode source-drain follower has the merit of small cell size. The chip was fabricated using 1.2μm standard CMOS technology, and a wide range of operation between 1nW and 100μW was demonstrated. The accuracy of the voltage follower was 30mV using minimum sized transistors, due to the variation of threshold voltage. The error in the output except for the threshold voltage mismatch was less than 10mV. The temperature dependence of the output was 0.11mV/°C. To improve the input voltage range and accuracy, non-constant biased cascode source-drain follower is examined. The sensor cell is designed for 10mV accuracy and the cell size is 105.3μm×81.4μm in 1.2μm CMOS design rules. The sensor cell was fabricated and showed that the error in the output except for the threshold voltage mismatch was less than 2mV in a range of total current between 3nA and 10μA and in a temperature range between 30°C and 100°C.

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A differential LC-VCO that adopts a transformer with asymmetric turns-ratio has been proposed. The asymmetric turns-ratio of the transformer leads to the suppression of the AM to FM conversion which is caused by the 1/f noise of the current source transistor. The analysis of the proposed scheme and the improvement in phase noise compare to conventional CMOS LC-VCOs are described. The transformer used in proposed VCO occupies about 430×430μm² of silicon area while the inductor in compared conventional VCO does 390×390μm².

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In this letter, a genetic programming method is used to synthesize filters. In order to improve the group delay characteristics, we propose a novel two-stage fitness function reflecting not only the frequency response but also the group delay characteristics of the evolved filters. We also deal with two practical design considerations, i. e., the filters include parasitic effects and are composed of elements with discrete values. The proposed method is applied to low-pass filter design cases. The experimental results show the method can effectively generate filters satisfying the design considerations and possessing improved group delay characteristics when compared with traditional filters.

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Two phase detectors (PD) are proposed to minimize the phase offset and deadzone when used in DLL or PLL. With the shortest symmetrical racing paths from both inputs, the binary PD achieves fast latch operation and theoretical elimination of the setup time. In contrast to the conventional PDs whose offsets are around 10ps with large sensitivity to sizing, the proposed binary PD shows an offset of less than 1ps with a reduction of 30-percent delay time. The proposed latch-type binary phase detection is also expanded to form a linear PD by the addition of a reset-generating circuit.

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