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IEICE Transactions on Electronics
Vol. E93.C (2010) No. 2 P 172-181

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http://doi.org/10.1587/transele.E93.C.172

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In this paper, a design methodology for the minimization of various performance metrics of MOS Current-Mode Logic (MCML) circuits is described. In particular, it allows to minimize the delay under a given power consumption, the power consumption under a given delay and the power-delay product. Design solutions can be evaluated graphically or by simple and effective automatic procedures implemented within the MATLAB environment. The methodology exploits the novel concepts of crossing-point current and crossing-point capacitance. A useful feature of it is that it provides the designer with useful insights into the dependence of the performance metrics on design variables and fan-out capacitance. The methodology was validated by designing several MCML circuits in an IBM 130nm CMOS process.

Copyright © 2010 The Institute of Electronics, Information and Communication Engineers

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