A Cascaded Folding ADC Based on Fast-Settling 3-Degree Folders with Enhanced Reset Technique

Koichi ONO; Takeshi OHKAWA; Masahiro SEGAMI; Masao HOTTA

doi:10.1587/transele.E93.C.288

IEICE Transactions on Electronics

Online ISSN : 1745-1353
Print ISSN : 0916-8524

Special Section on Circuits and Design Techniques for Advanced Large Scale Integration

A Cascaded Folding ADC Based on Fast-Settling 3-Degree Folders with Enhanced Reset Technique

Koichi ONO, Takeshi OHKAWA, Masahiro SEGAMI, Masao HOTTA

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Keywords: ADC, folding, interpolation, reset, averaging, error correction

JOURNAL RESTRICTED ACCESS

2010 Volume E93.C Issue 3 Pages 288-294

DOI https://doi.org/10.1587/transele.E93.C.288

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Abstract

A 7bit 1.0Gsps Cascaded Folding ADC is presented. This ADC employs cascaded folding architecture with 3-degree folders. A new reset technique and layout shuffling enable the ADC to operate at high-speed with low power consumption. Implemented in a 90nm CMOS process technology the ADC consumes 230mW with 1.2V and 2.5V supplies and has a SNR of 38dB.

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