A 4Gb/s Adaptive FFE/DFE Receiver with a Data-Dependent Jitter Measurement

Abstract

This paper presents an adaptive FFE/DFE receiver with an algorithm that measures the data-dependent jitter. The proposed adaptive algorithm determines the compensation level by measuring the input data-dependent jitter. The adaptive algorithm is combined with a clock and data recovery phase detector. The receiver is fabricated in with 0.13µm CMOS technology, and the compensation range of equalization is up to 26dB at 2GHz. The test chip is verified for a 40 inch FR4 trace and a 53cm flexible printed circuit channel. The receiver occupies an area of 440µm × 520µm and has a power dissipation of 49mW (excluding the I/O buffers) from a 1.2V supply.