抄録
A novel charge-recovery logic structure called Pulse Boost Logic (PBL) is proposed in this paper. PBL is a high-speed low-energy-dissipation charge-recovery logic with dual-rail evaluation tree structure. It is driven by 2-phase non-overlap clock, and requires no DC power supply. PBL belongs to boost logic family, which includes boost logic, enhanced boost logic and subthreshold boost logic. In this paper, PBL has been compared with other charge-recovery logic technologies. To demonstrate the performance of PBL structure, a 4-bit pipeline multiplier is designed and fabricated with 0.18µm CMOS process technology. The simulation results indicate that the 4-bit multiplier can work at a frequency of 1.8GHz, while the measurement of test chip is at operation frequency of 161MHz, and the power dissipation at 161MHz is 772µW.
