IEICE Transactions on Electronics
Online ISSN : 1745-1353
Print ISSN : 0916-8524
Special Section on Solid-State Circuit Design - Architecture, Circuit, Device and Design Methodology
Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling
Benjamin DEVLINMakoto IKEDAKunihiro ASADA
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2012 Volume E95.C Issue 4 Pages 546-554

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Abstract

A 65nm self synchronous field programmable gate array (SSFPGA) which uses autonomous gate-level power gating with minimal control circuitry overhead for energy minimum operation is presented. The use of self synchronous signaling allows the FPGA to operate at voltages down to 370mV without any parameter tuning. We show both 2.6x total energy reduction and 6.4x performance improvement at the same time for energy minimum operation compared to the non-power gated SSFPGA, and compared to the latest research 1.8x improvement in power-delay product (PDP) and 2x performance improvement. When compared to a synchronous FPGA in a similar process we are able to show up to 84.6x PDP improvement. We also show energy minimum operation for maximum throughput on the power gated SSFPGA is achieved at 0.6V, 27fJ/operation at 264MHz.

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© 2012 The Institute of Electronics, Information and Communication Engineers
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