A 0.15-µm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme

Shunsuke OKUMURA; Hidehiro FUJIWARA; Kosuke YAMAGUCHI; Shusuke YOSHIMOTO; Masahiko YOSHIMOTO; Hiroshi KAWAGUCHI

doi:10.1587/transele.E95.C.579

Special Section on Solid-State Circuit Design - Architecture, Circuit, Device and Design Methodology

A 0.15-µm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme

Shunsuke OKUMURA, Hidehiro FUJIWARA, Kosuke YAMAGUCHI, Shusuke YOSHIMOTO, Masahiko YOSHIMOTO, Hiroshi KAWAGUCHI

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Keywords: SRAM, FD-SOI, Inter-die variation

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2012 Volume E95.C Issue 4 Pages 579-585

DOI https://doi.org/10.1587/transele.E95.C.579

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Abstract

We propose a novel substrate-bias control scheme for an FD-SOI SRAM that suppresses inter-die variability. The proposed circuits detect inter-die threshold-voltage variation automatically, and then maximize read/write margins of memory cells to supply the substrate bias. We confirmed that a 486-kb 6T SRAM operates at 0.42V, in which an FS corner can be compared as much as 0.14V or more.

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