抄録
As an add-on device option for the ultra-low power CMOS technology, the double-gated vertical-channel Tunnel Field-Effect Transistors (TFETs) of different source configurations are comparatively studied from the perspectives of fabrication and current drivability. While the top-source design where the source of the device is placed on the top of the fin makes the fabrication and source engineering much easier, it is more susceptible to parasitic resistance issue. The bottom-source design is difficult to engineer the tunneling barrier and may require a special replacement technique. Examples of the schemes to engineer the tunneling barrier for the bottom-source TFET are suggested. A TCAD simulation study on the bottom-source devices shows that both the parasitic resistance of source region and the current enhancement mechanism by field coupling need be carefully considered in designing the source.
