Special Section on Fundamentals and Applications of Advanced Semiconductor Devices
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Tetsu KACHI
2012 年 E95.C 巻 5 号 p.
769
発行日: 2012/05/01
公開日: 2012/05/01
ジャーナル
認証あり
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Takaaki KOGA, Toru MATSUURA, Sébastien FANIEL, Satofumi SOUMA, ...
原稿種別: INVITED PAPER
2012 年 E95.C 巻 5 号 p.
770-776
発行日: 2012/05/01
公開日: 2012/05/01
ジャーナル
認証あり
We recently determined the values of intrinsic spin-orbit (SO) parameters for In
0.52Al
0.48As/In
0.53Ga
0.47As(10nm)/In
0.52Al
0.48As (InGaAs/InAlAs) quantum wells (QW), lattice-matched to (001) InP, from the weak localization/antilocalization analysis of the low-temperature magneto-conductivity measurements [1]. We have then studied the subband energy spectra for the InGaAs/InAlAs double QW system from beatings in the Shubnikov de Haas (SdH) oscillations. The basic properties obtained here for the double QW system provides useful information for realizing nonmagnetic spin-filter devices based on the spin-orbit interaction [2].
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Agnès TIXIER-MITA, Takuya TAKAHASHI, Hiroshi TOSHIYOSHI
原稿種別: INVITED PAPER
2012 年 E95.C 巻 5 号 p.
777-784
発行日: 2012/05/01
公開日: 2012/05/01
ジャーナル
認証あり
Chemical sensors are one of the oldest fields of research closely related to the semiconductor technology. From the Ion-Sensitive Field-Effect Transistors (ISFET) in the 70's, through Micro-Electro-Mechanical-System (MEMS) sensors from the end of the 80's, chemical sensors are combining in the 90's MEMS technology with LSI intelligence to devise more selective, sensitive and autonomous devices to analyse complex mixtures. A brief history of chemical sensors from the ISFET to the nowadays LSI integrated sensors is first detailed. Then the states-of-the-art of LSI integrated chemical sensors and their wide range of applications are discussed. Finally the authors propose a brand-new usage of integrated wireless MEMS sensors for remote surveillance of chemical substances, such as food-industry or pharmaceutical products, that are stored in closed environment like a bottle, for a long period. In such environment,
in-situ analyse is necessary, and electrical cables, for energy supply or data transfer, cannot be used. Thanks to integrated MEMS, an autonomous long-term
in-situ quality deterioration tracking system is possible.
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Yongho OH, Jae-Sung RIEH
原稿種別: PAPER
2012 年 E95.C 巻 5 号 p.
785-791
発行日: 2012/05/01
公開日: 2012/05/01
ジャーナル
認証あり
In this work, the effect of device dimension variation and metal wiring scheme on the RF performance of MOSFETs based on 0.13-µm RFCMOS technology has been investigated. Two sets of experiments have been carried out. In the first experiment, two types of source metal wiring options, each with various gate poly pitches, have been investigated. The results showed that the extrinsic capacitances (
Cegs,
Cegd) and parasitic resistances tend to increase with increasing gate poly pitch. Both cutoff frequency (
fT) and maximum oscillation frequency (
fmax) showed substantial degradation for the larger gate poly pitches. Based on measurement, we propose a simplified model for extrinsic parasitic capacitance as a function of gate poly pitch with different source metal wiring schemes. For the second experiment, the impact of gate metal wiring scheme and the number of gate fingers
Nf on the RF performance of MOSFET has been studied. Two different types of gate metal wiring schemes, one with poly layer and the other with M2 layer, are compared. The measurement showed that the capacitance is slightly increased, while gate resistance significantly reduced, with the M2 gate wiring. As a result,
fT is slightly degraded but
fmax is significantly improved, especially for larger
Nf, with the M2 gate wiring. The results in this work provide useful information regarding device dimension and metal wiring scheme for various RF applications of RF CMOS technology.
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Hyoungjun NA, Tetsuo ENDOH
原稿種別: PAPER
2012 年 E95.C 巻 5 号 p.
792-801
発行日: 2012/05/01
公開日: 2012/05/01
ジャーナル
認証あり
In this paper, a Schmitt Trigger based 10T SRAM (ST 10T SRAM) cell with the vertical MOSFET is proposed for low supply voltage operation, and its impacts on cell size, stability and speed performance are investigated. The proposed ST 10T SRAM cell with the vertical MOSFET achieves smaller cell size than the ST 10T SRAM cell with the conventional planar MOSFET. Moreover, the proposed SRAM cell realizes large and constant static noise margin (SNM) against bottom node resistance of the vertical MOSFET without any architectural changes from the present 6T SRAM architecture. The proposed SRAM cell also suppresses the degradation of the read time of the ST 10T SRAM cell due to the back-bias effect free characteristic of the vertical MOSFET. The proposed ST 10T SRAM cell with the vertical MOSFET is a superior SRAM cell for low supply voltage operation with a small cell size, stable operation, and fast speed performance with the present 6T SRAM architecture.
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Wen-Teng CHANG
原稿種別: PAPER
2012 年 E95.C 巻 5 号 p.
802-806
発行日: 2012/05/01
公開日: 2012/05/01
ジャーナル
認証あり
In the current study, stress-induced capacitance determined by direct measurement on MOSFETs was compared with that determined by indirect simulation through the delay of CMOS ring oscillators (ROs) fabricated side by side with MOSFETs. External compressive stresses were applied on <110> silicon-on-insulator (SOI) n-/p-MOSFETs with the ROs in a longitudinal configuration. The measured gate capacitance decreased as the compressive stress on SOI increased, which agrees with the result of the capacitance difference between measured and simulated delay of the ROs. The oscillation frequency shift of the ROs should mainly be attributed to oxide capacitance, aside from the change in mobility of the n-/p-MOSFETs. The result suggests that the stress-induced gate capacitance of partially depleted MOSFETs is an important factor for the capacitance shift in a circuit and that ROs can be used in a vehicle to determine mechanical stress-induced gate capacitance in MOSFETs.
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Takuya IMAMOTO, Tetsuo ENDOH
原稿種別: PAPER
2012 年 E95.C 巻 5 号 p.
807-813
発行日: 2012/05/01
公開日: 2012/05/01
ジャーナル
認証あり
In this paper, Source/Drain (
S/i>/D) engineering for high performance (HP) Vertical MOSFET (V-MOSFET) in 3Xnm generation and its beyond is investigated, by using gradual S/i>/D profile while degradation of driving current (ION) due to the parasitic series resistance (Rpara) is minimized through two-dimensional device simulation taking into account for gate-induced-drain-leakage (GIDL). In general, it is significant to reduce spreading resistance in the case of conventional Planar MOSFET. Therefore, in this study, we focused and analyzed the abruptness of diffusion layer that is still importance parameter in V-MOSFET. First, for improving the basic device performance such as subthreshold swing (SS), ION, and Rpara, S/D engineering is investigated. The dependency of device performance on S/D abruptness (σS/D) for various Lightly Doped Drain Extension (LDD) abruptness (σLDD) is analyzed. In this study, Spacer Length (LSP) is defined as a function of σS/D. As σS/D becomes smaller and S/D becomes more abrupt, LSP becomes shorter. SS depends on the σS/D rather than the σLDD. ION has the peak value of 1750µA/µm at σS/D =2nm/dec. and σLDD=3nm/dec. when the silicon pillar diameter (D) is 30nm and the gate length (Lg) is 60nm. As σS/D becomes small, higher ION is obtained due to reduction of Rpara while SS is degraded. However, when σS/D becomes too small in the short channel devices (Lg =60nm and Lg =45nm), ION is degraded because the leakage current due to GIDL is increased and reaches IOFF limit of 100nA/µm. In addition, as σLDD becomes larger, larger ION is obtained in the case of Lg =100nm and Lg =60nm because channel length becomes shorter. On the other hand, in the case of Lg =45nm, as σLDD becomes larger, ION is degraded because short channel effect (SCE) becomes significant. Next, the dependency of the basic device performance on D is investigated. By slimming D from 30nm to 10nm, while SS is improved and approaches the ideal value of 60mV/Decade, ION is degraded due to increase of on-resistance (Ron). From these results, it is necessary to reduce Rpara while IOFF meets limit of 100nA/µm for designing S/D of HP V-MOSFET. Especially for the V-MOSFET in the 1Xnm generation and its beyond, the influence of the Rpara and GIDL on ION becomes more significant, and therefore, the trade-off between σS/D and ION has a much greater impact on S/D engineering of V-MOSFET.
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Jae Sung LEE, In Man KANG
原稿種別: PAPER
2012 年 E95.C 巻 5 号 p.
814-819
発行日: 2012/05/01
公開日: 2012/05/01
ジャーナル
認証あり
Electrical performances of gate-all-around (GAA) tunneling field-effect transistors (TFETs) based on a silicon germanium (Si
1-xGe
x) layer have been investigated in terms of subthreshold swing (SS), on/off current ratio, on-state current (
Ion). Cut-off frequency (
fT) and maximum oscillation frequency (
fmax) were demonstrated from small-signal parameters such as effective gate resistance (
Rg), gate-drain capacitance (
Cgd), and transconductance (
gm). According to the technology computer-aided design (TCAD) simulation results, the current drivability,
fT, and
fmax of GAA TFETs based on Si
1-xGe
x layer were higher than those of GAA TFETs based on silicon. The simulated devices had 60nm channel length and 10nm channel radius. A GAA TFET with
x =0.4 had maximum
Ion of 51.4µA/µm, maximum
fT of 72GHz, and maximum
fmax of 610GHz. Additionally, improvements of performance at the presented device with PNPN junctions were demonstrated in terms of
Ion,
SS,
fT, and
fmax. When the device was designed with
x =0.4 and n
+ layer width (
Wn) =6nm, it shows
Ion of 271µA/µm,
fT of 245GHz, and
fmax of 1.49THz at an operating bias (
VGS=
VDS=1.0V).
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Hyungjin KIM, Min-Chul SUN, Hyun Woo KIM, Sang Wan KIM, Garam KIM, Byu ...
原稿種別: PAPER
2012 年 E95.C 巻 5 号 p.
820-825
発行日: 2012/05/01
公開日: 2012/05/01
ジャーナル
認証あり
Although the Tunnel Field-Effect Transistor (TFET) is a promising device for ultra-low power CMOS technology due to the ability to reduce power supply voltage and very small off-current, there have been few reports on the control of
VT for TFETs. Unfortunately, the TFET needs a different technique to adjust
VT than the MOSFET by channel doping because most of TFETs are fabricated on SOI substrates. In this paper, we propose a technique to control
VT of the TFET by putting an additional
VT-control doping region (VDR) between source and channel. We examine how much
VT is changed by doping concentration of VDR. The change of doping concentration modulates
VT because it changes the semiconductor work function difference,
φs,channel-
φs,source, at off-state. Also, the effect of the size of VDR is investigated. The region can be confined to the silicon surface because most of tunneling occurs at the surface. At the same time, we study the optimum width of this region while considering the mobility degradation by doping. Finally, the effect of the SOI thickness on the VDR adjusted
VT of TFET is also investigated.
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Min-Chul SUN, Hyun Woo KIM, Sang Wan KIM, Garam KIM, Hyungjin KIM, Byu ...
原稿種別: PAPER
2012 年 E95.C 巻 5 号 p.
826-830
発行日: 2012/05/01
公開日: 2012/05/01
ジャーナル
認証あり
As an add-on device option for the ultra-low power CMOS technology, the double-gated vertical-channel Tunnel Field-Effect Transistors (TFETs) of different source configurations are comparatively studied from the perspectives of fabrication and current drivability. While the top-source design where the source of the device is placed on the top of the fin makes the fabrication and source engineering much easier, it is more susceptible to parasitic resistance issue. The bottom-source design is difficult to engineer the tunneling barrier and may require a special replacement technique. Examples of the schemes to engineer the tunneling barrier for the bottom-source TFET are suggested. A TCAD simulation study on the bottom-source devices shows that both the parasitic resistance of source region and the current enhancement mechanism by field coupling need be carefully considered in designing the source.
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Sang-Youl LEE, Seung-Dong YANG, Jae-Sub OH, Ho-Jin YUN, Kwang-Seok JEO ...
原稿種別: PAPER
2012 年 E95.C 巻 5 号 p.
831-836
発行日: 2012/05/01
公開日: 2012/05/01
ジャーナル
認証あり
In this paper, we fabricated a gate-all-around bandgap- engineered (BE) silicon-oxide-nitride-oxide-silicon (SONOS) and silicon-oxide-high-
k-oxide-silicon (SOHOS) flash memory device with a vertical silicon pillar type structure for a potential solution to scaling down. Silicon nitride (Si
3N
4) and hafnium oxide (HfO
2) were used as trapping layers in the SONOS and SOHOS devices, respectively. The BE-SOHOS device has better electrical characteristics such as a lower threshold voltage (
VTH) of 0.16V, a higher
gm.max of 0.593µA/V and on/off current ratio of 5.76×10
8, than the BE-SONOS device. The memory characteristics of the BE-SONOS device, such as program/erase speed (P/E speed), endurance, and data retention, were compared with those of the BE-SOHOS device. The measured data show that the BE-SONOS device has good memory characteristics, such as program speed and data retention. Compared with the BE-SONOS device, the erase speed is enhanced about five times in BE-SOHOS, while the program speed and data retention characteristic are slightly worse, which can be explained via the many interface traps between the trapping layer and the tunneling oxide.
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Se Hwan PARK, Yoon KIM, Wandong KIM, Joo Yun SEO, Hyungjin KIM, Byung- ...
原稿種別: PAPER
2012 年 E95.C 巻 5 号 p.
837-841
発行日: 2012/05/01
公開日: 2012/05/01
ジャーナル
認証あり
We propose a new three-dimensional (3D) NAND flash memory array having
Tied B
it-line and
Ground S
elect Transisto
r (TiGer) [1]. Channels are stacked in the vertical direction to increase the memory density without the device size scaling. To distinguish stacked channels, a novel operation scheme is introduced instead of adding supplementary control gates. The stacked layers are selected by using ground select line (GSL) and common source line (CSL). Device structure and fabrication process are described. Operation scheme and simulation results for program inhibition are also discussed.
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Kyung-Chang RYOO, Jeong-Hoon OH, Sunghun JUNG, Hyungjin KIM, Byung-Goo ...
原稿種別: PAPER
2012 年 E95.C 巻 5 号 p.
842-846
発行日: 2012/05/01
公開日: 2012/05/01
ジャーナル
認証あり
Effects of conductive defects on unipolar resistive random access memory (RRAM) are investigated in order to reduce the operation current for high density and low power RRAM applications. It is clarified that forming voltage decreases with increasing charged conductive defects which are a source of conductive filament (CF) path and with decreasing cell thickness. Random circuit breaker (RCB) network simulation model which is a dynamic percolation simulation model is used to elucidate these effects. From this simulation results, the optimal cell thickness with sufficient conductive defect shows improved resistive switching characteristics such as low forming voltage, small set voltage distribution and low reset current. From the deep understanding of relationship between conductive defect in various cell thickness and other resistive switching parameters, RRAM with low forming voltage and reset current can be obtained and it will be one of the most promising next generation nonvolatile memories.
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Yuto NORIFUSA, Tetsuo ENDOH
原稿種別: PAPER
2012 年 E95.C 巻 5 号 p.
847-853
発行日: 2012/05/01
公開日: 2012/05/01
ジャーナル
認証あり
The performances of the conventional planar type 1T DRAM and the Vertical type 1T DRAM are compared based on structure difference using a fully-consistent device simulator. We discuss the structural advantage of the Vertical type 1T-DRAM in comparison with the conventional planar type 1T-DRAM, and evaluate their performance in each operating mode such as write, erase, read, and hold; and discuss its cell performances such as Cell Current Margin and data retention. These results provide a useful guideline designing the high performance Vertical type 1T-DRAM cell.
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Shuta TOGASHI, Takashi OHSAWA, Tetsuo ENDOH
原稿種別: PAPER
2012 年 E95.C 巻 5 号 p.
854-859
発行日: 2012/05/01
公開日: 2012/05/01
ジャーナル
認証あり
In this paper, we propose a new low power nonvolatile counter unit based on Magnetic Tunnel Junction (MTJ) with fine-grained power gating. The proposed counter unit consists of only a single latch with two MTJs. We verify the basic operation and estimate the power consumption of the proposed counter unit. The operating power consumption of the proposed nonvolatile counter unit is smaller than the conventional one below 140kHz. The power of the proposed unit is 74.6% smaller than the conventional one at low frequency.
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Woo Young KIM, Hee Chul LEE
原稿種別: PAPER
2012 年 E95.C 巻 5 号 p.
860-864
発行日: 2012/05/01
公開日: 2012/05/01
ジャーナル
認証あり
In this paper, a 60nm-thick ferroelectric film of poly(vinylidene fluoride-trifluoroethylene) on a flexible substrate of aluminum foil was fabricated and characterized. Compared to pristine silicon wafer, Al-foil has very large root-mean-square (RMS) roughness, thus presenting challenges for the fabrication of flat and uniform electronic devices on such a rough substrate. In particular, RMS roughness affects the leakage current of dielectrics, the uniformity of devices, and the switching time in ferroelectrics. To avoid these kinds of problems, a new thin film fabrication method adopting a detach-and-transfer technique has been developed. Here, ‘detach’ means that the ferroelectric film is detached from a flat substrate (sacrificial substrate), and ‘transfer’ refers to the process of the detached film being moved onto the rough substrate (main substrate). To characterize the dielectric property of the transferred film, polarization and voltage relationships were measured, and the results showed that a hysteresis loop could be obtained with low leakage current.
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Mingu JO, Yuki KATO, Masashi ARITA, Yukinori ONO, Akira FUJIWARA, Hiro ...
原稿種別: PAPER
2012 年 E95.C 巻 5 号 p.
865-870
発行日: 2012/05/01
公開日: 2012/05/01
ジャーナル
認証あり
We developed a flexible-logic-gate single-electron device (SED) in which logic functions can be selected by changing the voltage applied to the control gate. It consists of an array of nanodots with multiple inputs and multiple outputs. Since the gate electrodes couple capacitively to the many dots underneath, complicated characteristics depending on the combination of the gate voltages yield a selectable logic gate when some of the gate electrodes are used as control gates. One of the important issues is how to design the arrangement of nanodots and gate electrodes. In this study, we fabricated a Si nanodot array with two simple input gates and two output terminals, in which each gate was coupled to half of the nanodot array. Even though the device had a very simple input-gate arrangement and just one control gate, we could create a half-adder function through the use of current maps as functions of the input gate voltages. We found that the nanodots evenly coupled capacitively to both input gates played an important role in getting a basic set of logic functions. Moreover, these results guarantee that a more complicated input-gate structure, in which each gate evenly couples many nanodots, will yield more complicated functions.
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Masanari FUJITA, Mitsufumi SAITO, Michihiko SUHARA
原稿種別: PAPER
2012 年 E95.C 巻 5 号 p.
871-878
発行日: 2012/05/01
公開日: 2012/05/01
ジャーナル
認証あり
In this paper, we analyze current-voltage characteristics of InSb/AlInSb triple-barrier resonant tunneling diodes (TBRTDs) with spin-splitting under zero magnetic fields. The InSb has very small effective mass, thus we can obtain large spin-splitting by Rashba spin-orbit interaction due to asymmetric InSb/AlInSb quantum wells. In our model, broadening of each resonant tunneling level and spin-splitting energy can be considered to calculate spin-polarized resonant tunneling current.
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Akio OHTA, Yuta GOTO, Shingo NISHIGAKI, Guobin WEI, Hideki MURAKAMI, S ...
原稿種別: PAPER
2012 年 E95.C 巻 5 号 p.
879-884
発行日: 2012/05/01
公開日: 2012/05/01
ジャーナル
認証あり
We have studied resistance-switching properties of RF sputtered Si-rich oxides sandwiching with Pt electrodes. By sweeping bias to the top Pt electrode, non-polar type resistance switching was observed after a forming process. In comparison to RF sputtered TiO
x case, significant small current levels were obtained in both the high resistance state (HRS) and the low resistance state (LRS). And, even with decreasing SiO
x thickness down to ∼8nm from 40nm, the ON/OFF ratio in resistance-switching between HRS and LRS as large as ∼10
3 was maintained. From the analysis of current-voltage characteristics for Pt/SiO
x on p-type Si(100) and n-type Si(100), it is suggested that the red-ox (REDction and OXidation) reaction induced by electron fluence near the Pt/SiO
x interface is of importance for obtaining the resistance-switching behavior.
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Min LIAO, Hiroshi ISHIWARA, Shun-ichiro OHMI
原稿種別: PAPER
2012 年 E95.C 巻 5 号 p.
885-890
発行日: 2012/05/01
公開日: 2012/05/01
ジャーナル
認証あり
Pentacene-based organic field-effect transistors (OFETs) with SiO
2 and HfON gate insulators have been fabricated, and the effect of gate insulator on the electrical properties of pentacene-based OFETs and the microstructures of pentacene films were investigated. It was found that the grain size for pentacene film deposited on HfON gate insulator is larger than that for pentacene film deposited on SiO
2 gate insulator. Due to the larger grain size, pentacene-based OFET with HfON gate insulator shows better electrical properties compared to pentacene-based OFET with SiO
2 gate insulator. Meanwhile, low-temperature (such as 140°C) fabricated pentacene-based OFET with HfON gate insulator was also investigated. The OFET fabricated at 140°C shows a small subthreshold swing of 0.14V/decade, a large on/off current ratio of 4×10
4, a threshold voltage of -0.65V, and a hole mobility of 0.33cm
2/Vs at an operating voltage of -2V.
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Moon-Sik SEO, Tetsuo ENDOH
原稿種別: PAPER
2012 年 E95.C 巻 5 号 p.
891-897
発行日: 2012/05/01
公開日: 2012/05/01
ジャーナル
認証あり
Recently, the 3-D vertical Floating Gate (FG) type NAND cell arrays with the Sidewall Control Gate (SCG), such as ESCG, DC-SF and S-SCG, are receiving attention to overcome the reliability issues of Charge Trap (CT) type device. Using this novel cell structure, highly reliable flash cell operations were successfully implemented without interference effect on the FG type cell. However, the 3-D vertical FG type cell has large cell size by about 60% for the cylindrical FG structure. In this point of view, we intensively investigate the scalability of the FG width of the 3-D vertical FG NAND cells. In case of the planar FG type NAND cell, the FG height cannot be scaled down due to the necessity of obtaining sufficient coupling ratio and high program speed. In contrast, for the 3-D vertical FG NAND with SCG, the FG is formed cylindrically, which is fully covered with surrounded CG, and very high CG coupling ratio can be achieved. As results, the scaling of FG width of the 3-D vertical FG NAND cell with S-SCG can be successfully demonstrated at 10nm regime, which is almost the same as the CT layer of recent BE-SONOS NAND.
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Sang-Baie SHIN, Ko-Ichiro IIJIMA, Hiroshi OKADA, Sho IWAYAMA, Akihiro ...
原稿種別: PAPER
2012 年 E95.C 巻 5 号 p.
898-903
発行日: 2012/05/01
公開日: 2012/05/01
ジャーナル
認証あり
In this paper, we designed and fabricated large scale micro-light-emitting-diode (LED) arrays and silicon driver for single chip device for realizing as prototypes of heterogeneous optoelectronic integrated circuits (OEICs). The large scale micro-LED arrays were separated by a dry etching method from mesa structure to 16,384 pixels of 128 × 128, each with a size of 15µm in radius. Silicon driver was designed the additional bonding pad on each driving transistor for bonding with micro-LED arrays. Fabricated micro-LED arrays and driver were flip-chip bonded using anisotropic conductive adhesive.
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Atsushi KATO, Toru KANAZAWA, Shunsuke IKEDA, Yoshiharu YONAI, Yasuyuki ...
原稿種別: PAPER
2012 年 E95.C 巻 5 号 p.
904-909
発行日: 2012/05/01
公開日: 2012/05/01
ジャーナル
認証あり
In this paper, we report a reduction in the access resistance of InP/InGaAs composite-channel metal-oxide-semiconductor field-effect-transistors (MOSFETs) with a back-source electrode. The source region has two electrodes. The source electrode on the surface side is connected to the channel through a doped layer and supplies the electrons. The back-source electrode is constructed under the channel layer and is insulated from the doped layer in order to avoid current leakage. The function of the back-source electrode is to increase the carrier concentration in the channel layer of the source region. In the simulation, the electron density in the channel layer is almost doubled by the effect of the back-source voltage. The fabricated III-V MOSFET has a channel length of 6 µm. A 6% increase in the maximum drain current density (
Id) and a 6.8% increase in the transconductance (
gm) (
Vd=2V) are observed. The increase in the carrier density in the channel is estimated to be 20% when the applied voltage of the back-source electrode is 6V.
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Gibong LEE, Woo Young CHOI
原稿種別: BRIEF PAPER
2012 年 E95.C 巻 5 号 p.
910-913
発行日: 2012/05/01
公開日: 2012/05/01
ジャーナル
認証あり
We have investigated the low-power circuit applicability of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs). Based on the device-level comparison of HG, SiO
2-only and high-
k-only TFETs, their circuit performance and energy consumption have been discussed. It has been shown that HG TFETs can deliver ∼ 14400x higher performance than the SiO
2-only TFETs and ∼ 17x higher performance than the high-
k-only TFETs due to its higher on current and lower capacitance at the same static power, same power supply. It has been revealed that HG TFETs have better voltage scalability than the others. It is because HG TFETs dissipate only ∼8% of energy consumption of SiO
2-only TFETs and ∼17% of that of high-
k-only TFETs under the same performance condition.
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Boram HAN, Woo Young CHOI
原稿種別: BRIEF PAPER
2012 年 E95.C 巻 5 号 p.
914-916
発行日: 2012/05/01
公開日: 2012/05/01
ジャーナル
認証あり
The fringe field effects of nano-electromechanical (NEM) nonvolatile memory cells have been investigated analytically for the accurate evaluation of NEM memory cells. As the beam width is scaled down, fringe field effect becomes more severe. It has been observed that pull-in, release and hysteresis voltage decrease more than our prediction. Also, the fringe field on cell characteristics has been discussed.
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Naoaki TAKEBE, Yasuyuki MIYAMOTO
原稿種別: BRIEF PAPER
2012 年 E95.C 巻 5 号 p.
917-920
発行日: 2012/05/01
公開日: 2012/05/01
ジャーナル
認証あり
In this paper, we report the reduction in the base-collector capacitance (C
BC) of InP/InGaAs double heterojunction bipolar transistors with buried SiO
2 wires (BG-HBT). In a previous trial, we could not confirm a clear difference between the C
BC of the conventional HBT and that of the BG-HBT because the subcollector layer was thicker than expected. In this study, the interface between the collector and the subcollector was shifted to the middle of the SiO
2 wires by adjusting the growth temperature, and a reduction in C
BC with buried SiO
2 wires was confirmed. The estimated C
BC of the BG-HBT was 7.6fF, while that of the conventional HBT was 8.6fF. This 12% reduction was in agreement with the 10% reduction calculated according to the designed size.
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Daeho YUN, Bongsub SONG, Kyunghoon KIM, Junan LEE, Jinwook BURM
原稿種別: BRIEF PAPER
2012 年 E95.C 巻 5 号 p.
921-923
発行日: 2012/05/01
公開日: 2012/05/01
ジャーナル
認証あり
A low-power switching method using a bootstrapping circuit is proposed for a high-speed output driver of transmitter. Compared with a conventional output driver, the proposed scheme employs only nMOSFETs to transmit data. The bootstrapping circuit ensures the proper switching of nMOSFET. The proposed scheme is simulated and fabricated using a 0.18µm CMOS technology, showing 10.2% lower power consumption than a conventional switching driver at 2.5Gb/s data rate.
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Hiroya IKEDA, Faiz SALLEH
原稿種別: BRIEF PAPER
2012 年 E95.C 巻 5 号 p.
924-927
発行日: 2012/05/01
公開日: 2012/05/01
ジャーナル
認証あり
We herein investigate the operation stability of the single-electron-pump (SEP) refrigerator with respect to thermal and dimensional fluctuations. The SEP refrigerator was found to successfully demonstrate single-electron extraction and injection at temperatures up to 2K. Although the dimensional fluctuation in junction capacitance will seriously affect operation, the effect of the gate capacitance fluctuation is unlikely to be severe.
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Takayuki KOHAMA, Makoto ANDO
原稿種別: PAPER
専門分野: Electromagnetic Theory
2012 年 E95.C 巻 5 号 p.
928-935
発行日: 2012/05/01
公開日: 2012/05/01
ジャーナル
認証あり
Radiation integral areas are localized and reduced based upon the locality of scattering phenomena. In the high frequency, the scattering field is given by the currents, not the entire region, but on the local areas near the scattering centers, such as the stationary phase points and edge diffraction points, due to the cancelling effect of integrand in the radiation integral. The numerical calculation which this locality is implemented into has been proposed for 2-dimensional problems. The scattering field can be approximated by integrating the currents weighted by the adequate function in the local areas whose size and position are determined appropriately. Fresnel zone was previously introduced as the good criterion to determine the local areas, but the determination method was slightly different, depending on the type of scattering centers. The objective of this paper is to advance the Fresnel zone criteria in a 2-dimensional case to the next stage with enhanced generality and applicability. The Fresnel zone number is applied not directly to the actual surface but to the virtual one associated with the modified surface-normal vector satisfying the reflection law. At the same time, the argument in the weighting function is newly defined by the Fresnel zone number instead of the actual distance from the scattering centers. These two revisions bring about the following three advantages; the uniform treatment of various types scattering centers, the smallest area in the localization and applicability to 3-dimensional problems.
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Le Ngoc SON, Takashi TACHIKI, Takashi UCHIDA, Yoshizumi YASUOKA
原稿種別: PAPER
専門分野: Microwaves, Millimeter-Waves
2012 年 E95.C 巻 5 号 p.
936-941
発行日: 2012/05/01
公開日: 2012/05/01
ジャーナル
認証あり
Thin-film 2-arm Archimedean spiral antenna coupled with a bismuth (Bi) microbolometer was fabricated on a fused quartz substrate backed by cupper (Cu) plate reflector. Antenna patterns of the device agreed with the theoretical patterns derived from the imaging force model at 100GHz band. The detected voltages of the antenna exhibited a periodic variation with changing the thickness of the substrate. The maximum and minimum detected voltages were obtained when the substrate thickness was odd and even integer multiples of a quarter of the wavelength in the substrate, respectively. Furthermore, the detected voltages were almost constant within the change of ∼3dB ranging from 76.9 to 106.8GHz. The wide band characteristic of the antenna was obtained.
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Qinghong BU, Ning LI, Kenichi OKADA, Akira MATSUZAWA
原稿種別: PAPER
専門分野: Microwaves, Millimeter-Waves
2012 年 E95.C 巻 5 号 p.
942-948
発行日: 2012/05/01
公開日: 2012/05/01
ジャーナル
認証あり
This paper presents the evaluation of the L-2L de-embedding method with misalignment of the contact position. The issues of misalignment of the contact position are investigated. The analysis of misalignment in the L-2L de-embedding procedure is performed. Two comparisons are carried out to verify the error of the L-2L de-embedding method. The calculation percent error in quality factor of the transmission line becomes up to 9.0%, while the transistor S-parameter error percentage becomes up to 21% at 60GHz in the experimental results. The results show that the measurement errors, caused by the misalignment of the contact position, should be considered carefully.
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Hundo SHIN, Seung-Tak RYU
原稿種別: PAPER
専門分野: Electronic Circuits
2012 年 E95.C 巻 5 号 p.
949-957
発行日: 2012/05/01
公開日: 2012/05/01
ジャーナル
認証あり
This paper proposes a new biquad structure based on a flipped voltage follower (FVF) for low-power and wide-bandwidth (BW) low pass filter. The proposed biquad structure consists of an FVF and a source follower (SF) for complex pole pair generation and zero cancellation. The presented design provides good linearity at low power consumption, owing to the voltage follower structures. A power/BW ratio (PBWR) is suggested as a performance metric to compare power efficiency to bandwidth, and the proposed biquad structure shows excellent PBWR, especially for low quality factor (
Q) design. As a prototype, a fourth order Bessel filter was fabricated in 0.18µm CMOS technology. The measured BW, power consumption, IIP3, and FoM are 120MHz, 180µW, 15dBm, and 0.34fJ, respectively.
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Bhum Jae SHIN, Hyung Dal PARK, Heung-Sik TAE
原稿種別: PAPER
専門分野: Electronic Displays
2012 年 E95.C 巻 5 号 p.
958-963
発行日: 2012/05/01
公開日: 2012/05/01
ジャーナル
認証あり
In order to improve the address discharge characteristics, we propose the modified selective reset waveform utilizing the address-bias voltage (
Va-bias) during the ramp-up period. It is revealed that the proper
Va-bias makes the weak discharge between the address and scan electrodes which plays a role in sufficiently removing the wall charge, thereby contributing to minimizing the wall-voltage variation during the address-period. As a result of adopting the
Va-bias in the conventional selective reset driving waveform, it was found that the address discharge delay time can be shortened by approximately 40ns and the address period of each subfield can be significantly reduced by about 43µs.
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Jongsik LIM, Yuckhwan JEON, Sang-Min HAN, Yongchae JEONG, Dal AHN
原稿種別: BRIEF PAPER
専門分野: Microwaves, Millimeter-Waves
2012 年 E95.C 巻 5 号 p.
964-967
発行日: 2012/05/01
公開日: 2012/05/01
ジャーナル
認証あり
A design of dual band amplifier using composite right/left handed (CRLH) transmission line structure is described. First, two single-band matching networks are designed for two frequencies, and they are synthesized into one dual band matching network. It is shown that CRLH transmission lines with arbitrary dual frequencies and dual electrical lengths can be designed. The CRLH transmission line section for the dual band matching network is implemented by lumped inductors and capacitors as the left handed (LH) section, and normal transmission line elements as the right handed (RH) section. As an example, a dual band amplifier for 1800MHz and 2300MHz is designed and measured. The simulated and measured performances well verify the proposed design by showing good matching and gain responses at the desired frequencies.
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Seunghyeon KIM, Hyunchol SHIN
原稿種別: BRIEF PAPER
専門分野: Electronic Circuits
2012 年 E95.C 巻 5 号 p.
968-971
発行日: 2012/05/01
公開日: 2012/05/01
ジャーナル
認証あり
A sub-mW current-reuse CMOS VCO is presented for wireless sensor network applications. In order to break the interdependence between the current consumption and the phase noise performance in the conventional current-reuse structure, a tail current source is added to the switching core in such a way that they are simultaneously switched during operation. With this, the current consumption can be maintained at a minimum level while the FET size can be optimally determined for large swing and good phase noise performances. The proposed VCO's advantage of achieving low phase noise at low current consumption is clearly demonstrated by simulations in comparison to the conventional structure. The proposed VCO is implemented in 0.13µm CMOS. It dissipates 0.6mW from 1.2V supply. The measured phase noise at the output frequency of 2.28GHz is -121dBc/Hz at 1MHz offset.
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Jhin-Fang HUANG, Wen-Cheng LAI, Kun-Jie HUANG, Ron-Yi LIU
原稿種別: BRIEF PAPER
専門分野: Electronic Circuits
2012 年 E95.C 巻 5 号 p.
972-975
発行日: 2012/05/01
公開日: 2012/05/01
ジャーナル
認証あり
In this paper, a fifth order curer low-pass filter using as switched-capacitor (SC) architecture is proposed and fabricated with TSMC 0.18µm CMOS process. A fully differential SC is adopted via the bilinear transform of the corresponding analogue RLC passive prototype. To reach the largest possible input dynamic range and save chip area, the method of dynamic range scaling and minimum capacitor scaling is used. Measured results show that the proposed filter achieves a pass-band of 12.1MHz with a sampling rate of 100MHz, a SFDR of 50dB, a stop-band attenuation greater than 50dB and a power consumption of 48.5mW at 1.8V power supply. Including pads, the chip area occupies 1.515 (1.39×1.09)mm
2. This paper has the feature of low noise, excellent linearity of the filter, and high stability. The experimental results show that it has perfect performance for WiMAX applications and standard is recommended.
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