Circuit Techniques to Enhance Linearity and Intrinsic Gain to Realize a 1.2V, 200MHz, +10.3dBm IIP3 and 7th-Order LPF in a 65nm CMOS

抄録

Circuit techniques to enhance the linearity of input-voltage-to-current (V/I) conversion and to increase the output impedance of a current source by compensating for the low intrinsic gain of a transistor were introduced to realize a high-frequency operational transconductance amplifier (OTA) for a low supply voltage using sub-100-nm CMOS processes. Applying these techniques, a MOS 7th-order Gm-C linear-phase low-pass filter (LPF) was realized using a 65nm CMOS process. A simplified biquad LPF that can serve as a component of a 7th-order LPF was newly developed by replacing OTAs with resistors. As a result, the -3dB frequency bandwidth, group delay ripple, 3rd-order distortion, and 3rd-order input intercept point (IIP3) were 200MHz, 2.2%, ≤ -55dB with a 100MHz input, and +10.3dBm, respectively, all with a ±0.1Vp-p input signal at each input terminal in the pseudodifferential configuration. The LPF including an output buffer dissipated 60mW in the case of a 1.2V supply. Wide spurious-free dynamic range (SFDR) characteristics were confirmed up to high frequencies.