IEICE Transactions on Electronics
Online ISSN : 1745-1353
Print ISSN : 0916-8524
Regular Section
Digital Background Calibration for a 14-bit 100-MS/s Pipelined ADC Using Signal-Dependent Dithering
Zhao-xin XIONGMin CAIXiao-Yong HEYun YANG
Author information
JOURNAL RESTRICTED ACCESS

2014 Volume E97.C Issue 3 Pages 207-214

Details
Abstract

A digital background calibration technique using signal-dependent dithering is proposed, to correct the nonlinear errors which results from capacitor mismatches and finite opamp gain in pipelined analog-to-digital converter (ADC). Large magnitude dithers are used to measure and correct both errors simultaneously in background. In the proposed calibration system, the 2.5-bit capacitor-flip-over multiplying digital-to-analog converter (MDAC) stage is modified for the injection of large magnitude dithering by adding six additional comparators, and thus only three correction parameters in every stage subjected to correction were measured and extracted by a simple calibration algorithm with multibit first stage. Behavioral simulation results show that, using the proposed calibration technique, the signal-to-noise-and-distortion ratio improves from 63.3 to 79.3dB and the spurious-free dynamic range is increased from 63.9 to 96.4dB after calibrating the first two stages, in a 14-bit 100-MS/s pipelined ADC with σ=0.2% capacitor mismatches and 60dB nonideal opamp gain. The time of calibrating the first two stages is around 1.34 seconds for the modeled ADC.

Information related to the author
© 2014 The Institute of Electronics, Information and Communication Engineers
Previous article Next article
feedback
Top