Address Power Reduction Method for High-Resolution Plasma Display Panels Using Address Data Smoothing Based on a Visual Masking Effect

抄録

This paper proposes an address power reduction method for plasma display panels (PDPs) using subfield data smoothing based on a visual masking effect. High-resolution, high-frame-rate PDPs have large address power loss caused by parasitic capacitance. Although the address power is reduced by smoothing the subfield data, noise is generated. The proposed method reduces the address power while maintaining the image quality by choosing the smoothing area of the address data based on the visual masking effect. The results of subjective assessment for the images based on smoothed address data indicate that image quality is maintained.