抄録
Unlimited requirements for system-on-chip (SoC) facilitate three-dimensional (3D) technology as a promising alternative for extending Moore's Law. In spite of many advantages 3D technology provides, 3D technology faces testing issues because of the complexity of 3D design. Therefore, resolving the problem of test optimization and reducing test cost are crucial challenges. In this paper, we propose a novel optimization mechanism of 3D SoCs to minimize test time for mid-bond testing. To make our proposed mechanism more practical, we discuss test cost in mid-bond testing with consideration of manufacturing influence factors. Experimental results on ITC'02 SoC benchmark circuits show that our proposed mechanism reduces mid-bond test time by around 73% on average compared with one baseline solution, furthermore, the mechanism also proves its capacity in test cost reduction.
