Compact Analytical Threshold Voltage Model of Strained Gate-All-Around MOSFET Fabricated on Si_1-xGe_x Virtual Substrate

抄録

In this paper, an analytical threshold voltage model of the strained gate-all-around MOSFET fabricated on the Si_1-xGe_x virtual substrate is presented by solving the two-dimensional Poisson equation. The impact of key parameters such as the strain, channel length, gate oxide thickness and radius of the silicon cylinder on the threshold voltage has been investigated. It has been demonstrated that the threshold voltage decreases as the strain in the channel increases. The threshold voltage roll-off becomes severe when increasing the Ge content in the Si_1-xGe_x virtual substrate. The model is found to tally well with the device simulator.