Design Optimization for Process-Variation-Tolerant 22-nm FinFET-Based 6-T SRAM Cell with Worst-Case Sampling Method

Sangheon OH; Changhwan SHIN

doi:10.1587/transele.E99.C.541

Special Section on Fundamentals and Applications of Advanced Semiconductor Devices

Design Optimization for Process-Variation-Tolerant 22-nm FinFET-Based 6-T SRAM Cell with Worst-Case Sampling Method

Sangheon OH, Changhwan SHIN

著者情報

キーワード: random variation, FinFET, SRAM, worst-case sampling

ジャーナル認証あり

2016 年 E99.C 巻 5 号 p. 541-543

DOI https://doi.org/10.1587/transele.E99.C.541

詳細

抄録

To find the optimal design in alleviating the effect of random variations on a SRAM cell, a worst-case sampling method is used. From the quantitative analysis using this method, the optimal designs for a process-variation-tolerant 22-nm FinFET-based 6-T SRAM cell are proposed and implemented through cell layouts and a dual-threshold-voltage designs.

責任著者(Corresponding author)

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