A 10-bit 20-MS/s Asynchronous SAR ADC with Meta-Stability Detector Using Replica Comparators

Sang-Min PARK; Yeon-Ho JEONG; Yu-Jeong HWANG; Pil-Ho LEE; Yeong-Woong KIM; Jisu SON; Han-Yeol LEE; Young-Chan JANG

doi:10.1587/transele.E99.C.651

Special Section on Analog Circuits and Related SoC Integration Technologies

A 10-bit 20-MS/s Asynchronous SAR ADC with Meta-Stability Detector Using Replica Comparators

Sang-Min PARK, Yeon-Ho JEONG, Yu-Jeong HWANG, Pil-Ho LEE, Yeong-Woong KIM, Jisu SON, Han-Yeol LEE, Young-Chan JANG

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Keywords: asynchronous successive approximation register, analog-to-digital converter, meta-stability detector, replica comparator

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2016 Volume E99.C Issue 6 Pages 651-654

DOI https://doi.org/10.1587/transele.E99.C.651

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Abstract

A 10-bit 20-MS/s asynchronous SAR ADC with a meta-stability detector using replica comparators is proposed. The proposed SAR ADC with the area of 0.093mm² is implemented using a 130-nm CMOS process with a 1.2-V supply. The measured peak ENOBs for the full rail-to-rail differential input signal is 9.6bits.

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