Simulation-Based Understanding of “Charge-Sharing Phenomenon” induced by Heavy-Ion incident on a 65nm Bulk CMOS Memory Circuit

Akifumi Maru; Akifumi Matsuda; Satoshi Kuboyama; Mamoru Yoshimoto

doi:10.1587/transele.2021ECS6008

This article has now been updated. Please use the final version.

Simulation-Based Understanding of “Charge-Sharing Phenomenon” induced by Heavy-Ion incident on a 65nm Bulk CMOS Memory Circuit

Akifumi Maru, Akifumi Matsuda, Satoshi Kuboyama, Mamoru Yoshimoto

Author information

Keywords: Single event upset, Charge sharing, Device simulation, 65 nm bulk CMOS memory

JOURNAL RESTRICTED ACCESS Advance online publication

Article ID: 2021ECS6008

DOI https://doi.org/10.1587/transele.2021ECS6008

The final version of this article is now available: Vol. E105.C (2022), No. 1 pp. 47-50

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Abstract

In order to expect the single event occurrence on highly integrated CMOS memory circuit, quantitative evaluation of charge sharing between memory cells is needed. In this study, charge sharing area induced by heavy ion incident is quantitatively calculated by using device-simulation-based method. The validity of this method is experimentally confirmed using the charged heavy ion accelerator.

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