IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Online ISSN : 1745-1337
Print ISSN : 0916-8508
Regular Section
Design of a High-Throughput Sliding Block Viterbi Decoder for IEEE 802.11ac WLAN Systems
Kai-Feng XIABin WUTao XIONGCheng-Ying CHEN
Author information
JOURNALS RESTRICTED ACCESS

2017 Volume E100.A Issue 8 Pages 1606-1614

Details
Abstract

This paper presents a high-throughput sliding block Viterbi decoder for IEEE 802.11ac systems. A 64-state bidirectional sliding block Viterbi method is proposed to meet the speed requirement of the system. The decoder throughput goes up to 640Mbps, which can be further increased by adding the block parallelism. Moreover, a modified add-compare-select (ACS) unit is designed to enhance the working frequency. The modified ACS unit obtains nearly 26% speed-up, compared to the conventional ACS unit. However, the area overhead and power dissipation are almost the same. The decoder is designed in a SMIC 0.13µm technology, and it occupies 1.96mm2 core area and 105mW power consumption with an energy efficiency of 0.1641nJ/bit with a 1.2V voltage supply.

Information related to the author
© 2017 The Institute of Electronics, Information and Communication Engineers
Next article
feedback
Top