IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Online ISSN : 1745-1337
Print ISSN : 0916-8508
Special Section on VLSI Design and CAD Algorithms
A Fast Three-Layer One-Side Bottleneck Channel Routing with Layout Constraints Using ILP
Kazuya TANIGUCHISatoshi TAYUAtsushi TAKAHASHIMathieu MOLONGOMakoto MINAMIKatsuya NISHIOKA
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2025 Volume E108.A Issue 3 Pages 509-516

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Abstract

An algorithm for three-layer bottleneck channel routing problem that uses ILP is proposed. The proposed algorithm determines the track and layer assignment of nets for problems with layout constraints in which pins of each net are placed on the upper boundary of the adjacent regions on both sides of the bottleneck channel. The proposed algorithm restricts the routing pattern of each net to one of three patterns by taking feasibility into account, and outputs a solution in a few seconds when the number of nets is 300.

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© 2025 The Institute of Electronics, Information and Communication Engineers
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