Timing Criticality for Timing Yield Optimization

Abstract

Block-based SSTA analyzes the timing variation of a chip caused by process variations effectively. However, block-based SSTA cannot identify critical nodes, nodes that highly influence the timing yield of a chip, used as the effective guidance of timing yield optimization. In this paper, we propose a new timing criticality to identify those nodes, referred to as the timing yield criticality (TYC). The proposed TYC is defined as the change in the timing yield, which is induced by the change in the mean arrival time at a node. For efficiency, we estimate the TYC through linear approximation instead of propagating the changed arrival time at a node to its fanouts. In experiments using the ISCAS 85 benchmark circuits, the proposed method estimated TYCs with the expense of 9.8% of the runtime for the exact computation. The proposed method identified the node that gives the greatest effect on the timing yield in all benchmark circuits, except C6288, while existing methods did not identify that for any circuit. In addition, the proposed method identified 98.4% of the critical nodes in the top 1% in the effect on the timing yield, while existing methods identified only about 10%.