IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Online ISSN : 1745-1337
Print ISSN : 0916-8508
Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa
Novel Register Sharing in Datapath for Structural Robustness against Delay Variation
Keisuke INOUEMineo KANEKOTsuyoshi IWAGAKI
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2008 Volume E91.A Issue 4 Pages 1044-1053

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Abstract

As the feature size of VLSI becomes smaller, delay variations become a serious problem in VLSI. In this paper, we propose a novel class of robustness for a datapath against delay variations, which is named structural robustness against delay variation (SRV), and propose sufficient conditions for a datapath to have SRV. A resultant circuit designed under these conditions has a larger timing margin to delay variations than previous designs without sacrificing effective computation time. In addition, under any degree of delay variations, we can always find an available clock frequency for a datapath having SRV property to operate correctly, which could be a preferable characteristic in IP-based design.

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© 2008 The Institute of Electronics, Information and Communication Engineers
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