IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Online ISSN : 1745-1337
Print ISSN : 0916-8508
Regular Section
A High-Speed Two-Parallel Radix-24 FFT/IFFT Processor for MB-OFDM UWB Systems
Jeesung LEEHanho LEE
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2008 Volume E91.A Issue 4 Pages 1206-1211

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Abstract

This paper presents a novel high-speed, low-complexity two-parallel 128-point radix-24 FFT/IFFT processor for MB-OFDM ultra-wideband (UWB) systems. The proposed high-speed, low-complexity FFT architecture can provide a higher throughput rate and low hardware complexity by using a two-parallel data-path scheme and a single-path delay-feedback (SDF) structure. The radix-24 FFT algorithm is also realized in our processor to reduce the number of complex multiplications. The proposed FFT/IFFT processor has been designed and implemented with 0.18μm CMOS technology in a supply voltage of 1.8V. The proposed two-parallel FFT/IFFT processor has a throughput rate of up to 900Msample/s at 450MHz while requiring much smaller hardware complexity and low power consumption.

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© 2008 The Institute of Electronics, Information and Communication Engineers
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