IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Online ISSN : 1745-1337
Print ISSN : 0916-8508
Regular Section
Low-Complexity Parallel Systolic Montgomery Multipliers over GF (2m) Using Toeplitz Matrix-Vector Representation
Chiou-Yng LEE
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2008 Volume E91.A Issue 6 Pages 1470-1477

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Abstract
In this paper, a generalized Montgomery multiplication algorithm in GF (2m) using the Toeplitz matrix-vector representation is presented. The hardware architectures derived from this algorithm provide low-complexity bit-parallel systolic multipliers with trinomials and pentanomials. The results reveal that our proposed multipliers reduce the space complexity of approximately 15% compared with an existing systolic Montgomery multiplier for trinomials. Moreover, the proposed architectures have the features of regularity, modularity, and local interconnection. Accordingly, they are well suited to VLSI implementation.
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© 2008 The Institute of Electronics, Information and Communication Engineers
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