Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin Model

Abstract

In deep submicron designs, predicting gate delays with interconnect load is a noteworthy work for Static Timing Analysis (STA). The effective capacitance C_eff concept and the Thevenin model that replaces the gate with a linear resistor and a voltage source are usually used to calculate the delay of gate with interconnect load. In conventional methods, it is not considered that the charges transferred into interconnect load and C_eff in the Thevenin model are not equal. The charge difference between interconnect load and C_eff has the large influence to the accuracy of computing C_eff. In this paper, an advanced effective capacitance model is proposed to consider the above problem in the Thevenin model, where the influence of the charge difference is modeled as one part of the effective capacitance to compute the gate delay. Experimental results show a significant improvement in accuracy when the charge difference between interconnect load and C_eff is considered.