IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Online ISSN : 1745-1337
Print ISSN : 0916-8508
Special Section on VLSI Design and CAD Algorithms
A System-Level Model of Design Space Exploration for a Tile-Based 3D Graphics SoC Refinement
Liang-Bi CHENChi-Tsai YEHHung-Yu CHENIng-Jer HUANG
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2009 Volume E92.A Issue 12 Pages 3193-3202

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Abstract

3D graphics application is widely used in consumer electronics which is an inevitable tendency in the future. In general, the higher abstraction level is used to model a complex system like 3D graphics SoC. However, the concerned issue is that how to use efficient methods to traverse design space hierarchically, reduce simulation time, and refine the performance fast. This paper demonstrates a system-level design space exploration model for a tile-based 3D graphics SoC refinement. This model uses UML tools which can assist designers to traverse the whole system and reduces simulation time dramatically by adopting SystemC. As a result, the system performance is improved 198% at geometry function and 69% at rendering function, respectively.

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© 2009 The Institute of Electronics, Information and Communication Engineers
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