High-Speed Two-Parallel Concatenated BCH-Based Super-FEC Architecture for Optical Communications

抄録

This paper presents a high-speed Forward Error Correction (FEC) architecture based on concatenated Bose-Chaudhuri-Hocquenghem (BCH) for 100-Gb/s optical communication systems. The concatenated BCH code consists of BCH(3860, 3824) and BCH(2040, 1930), which provides 7.98dB net coding gain at 10^-12 corrected bit error rate. The proposed BCH decoder features a low-complexity key equation solver using an error-locator computation RiBM (ECRiBM) algorithm and its architecture. The proposed concatenated BCH-based Super-FEC architecture has been implemented in 90-nm CMOS standard cell technology with a supply voltage of 1.1V. The implementation results show that the proposed architecture can operate at a clock frequency of 400MHz and has a throughput of 102.4-Gb/s for 90-nm CMOS technology.