IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Online ISSN : 1745-1337
Print ISSN : 0916-8508
Special Section on VLSI Design and CAD Algorithms
A 98 GMACs/W 32-Core Vector Processor in 65 nm CMOS
Xun HEXin JINMinghui WANGDajiang ZHOUSatoshi GOTO
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2011 Volume E94.A Issue 12 Pages 2609-2618

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Abstract

This paper presents a high-performance dual-issue 32-core SIMD platform for image and video processing. The SIMD cores support 8/16bits SIMD MAC instructions, and vertical vector access. Eight cores with a 4-ports L2 cache are connected by CIB bus as a cluster. Four clusters are connected by mesh network. This hierarchical network can provide more than 192GB/s low latency inter-core BW in average. The 4-ports L2 cache architecture is also designed to provide 192GB/s L2 cache BW. To reduce coherence operation in large-scale SMP, an application specified protocol is proposed. Compared with MOESI, 67.8% of L1 cache energy can be saved in 32 cores case. The whole system including 32 vector cores, 256KB L2 cache, 64-bit DDRII PHY and two PLL units, occupy 25mm2 in 65nm CMOS. It can achieve a peak performance of 375 GMACs and 98 GMACs/W at 1.2V.

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© 2011 The Institute of Electronics, Information and Communication Engineers
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