A 24dB Gain 51-68GHz Common Source Low Noise Amplifier Using Asymmetric-Layout Transistors

Abstract

At mm-wave frequency, the layout of CMOS transistors has a larger effect on the device performance than ever before in low frequency. In this work, the distance between the gate and drain contact (D_gd) has been enlarged to obtain a better maximum available gain (MAG). By using the asymmetric-layout transistor, a 0.6dB MAG improvement is realized when D_gd changes from 60nm to 200nm. A four-stage common-source low noise amplifier is implemented in a 65nm CMOS process. A measured peak power gain of 24dB is achieved with a power dissipation of 30mW from a 1.2-V power supply. An 18dB variable gain is also realized by adjusting the bias voltage. The measured 3-dB bandwidth is about 17GHz from 51GHz to 68GHz, and noise figure (NF) is from 4.0dB to 7.6dB.