IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Online ISSN : 1745-1337
Print ISSN : 0916-8508
Regular Section
An Improved Hybrid LUT-Based Architecture for Low-Error and Efficient Fixed-Width Squarer
Van-Phuc HOANGCong-Kha PHAM
Author information
JOURNALS RESTRICTED ACCESS

2012 Volume E95.A Issue 7 Pages 1180-1184

Details
Abstract

In this paper, an improved hybrid LUT-based architecture for low-error and efficient fixed-width squarer circuits is presented in which LUT-based and conventional logic circuits are employed together to achieve the good trade-off between hardware complexity and performance. By exploiting the mathematical identities and hybrid architecture, the mean error and mean squarer error of the proposed squarer are reduced by up to 40%, compared with the best previous method presented in literature. Moreover, the proposed method can improve the speed and reduce the area of the squarer circuit. The implementation and chip measurement results in 0.18-µm CMOS technology are also presented and discussed.

Information related to the author
© 2012 The Institute of Electronics, Information and Communication Engineers
Previous article Next article
feedback
Top