2013 Volume E96.A Issue 2 Pages 422-433
A 6-bit, 7mW, 700MS/s subranging ADC using Capacitive DAC (CDAC) and gate-weighted interpolation fabricated in 90nm CMOS technology is demonstrated. CDACs are used as a reference selection circuit instead of resistive DACs (RDAC) for reducing settling time and power dissipation. A gate-weighted interpolation scheme is also incorporated to the comparators, to reduce the circuit components, power dissipation and mismatch of conversion stages. By virtue of recent technology scaling, an interpolation can be realized in the saturation region with small error. A digital offset calibration technique using capacitor reduces comparator's offset voltage from 10mV to 1.5mV per sigma. Experimental results show that the proposed ADC achieves a SNDR of 34dB with calibration and FoM is 250fJ/conv., which is very attractive as an embedded IP for low power SoCs.
