Abstract
This paper presents a wide range in supply voltage, resolution, and sampling rate asynchronous successive approximation register (SAR) analog-to-digital converter (ADC). The proposed differential flip-flop in SAR logic and high efficiency wide range delay element extend the flexibility of speed and resolution tradeoff. The ADC fabricated in 40nm CMOS process covers 4-10bit resolution and 0.4-1V power supply range. The ADC achieved 49.8dB SNDR and the peak FoM of 3.4fJ/conv. with 160kS/sec at 0.4V single power supply voltage. At 10bit mode and 1V operation, up to 10MS/s, the FoM is below 10fJ/conv. while keeping ENOB of 8.7bit.