Abstract
This paper describes a soft-error tolerant and margin-enhanced nMOS-pMOS reversed 6T SRAM cell. The 6T SRAM bitcell comprises pMOS access and driver transistors, and nMOS load transistors. Therefore, the nMOS and pMOS masks are reversed in comparison with those of a conventional bitcell. In scaled process technology, The pMOS transistors present advantages of small random dopant fluctuation, strain-enhanced saturation current, and small soft-error sensitivity. The four-pMOS and two-nMOS structure improves the soft-error rate plus operating margin. We conduct SPICE and neutron-induced soft-error simulations to evaluate the n-p reversed 6T SRAM bitcell in 130-nm to 22-nm processes. At the 22-nm node, a multiple-cell-upset and single-bit-upset SERs are improved by 34% and 51% over a conventional 6T cell. Additionally, the static noise margin and read cell current are 2.04× and 2.81× improved by leveraging the pMOS benefits.
