IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Online ISSN : 1745-1337
Print ISSN : 0916-8508
Special Section on Design Methodologies for System on a Chip
Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization
Jun SHIOMITohru ISHIHARAHidetoshi ONODERA
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2015 Volume E98.A Issue 7 Pages 1455-1466

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Abstract

Near-threshold computing has emerged as one of the most promising solutions for enabling highly energy efficient and high performance computation of microprocessors. This paper proposes architecture-level statistical static timing analysis (SSTA) models for the near-threshold voltage computing where the path delay distribution is approximated as a lognormal distribution. First, we prove several important theorems that help consider architectural design strategies for high performance and energy efficient near-threshold computing. After that, we show the numerical experiments with Monte Carlo simulations using a commercial 28nm process technology model and demonstrate that the properties presented in the theorems hold for the practical near-threshold logic circuits.

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© 2015 The Institute of Electronics, Information and Communication Engineers
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