IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Online ISSN : 1745-1337
Print ISSN : 0916-8508
Special Section on Analog Circuit Techniques and Related Topics
0.5-V Sub-ns Open-BL SRAM Array with Mid-Point-Sensing Multi-Power-Supply 5T Cell
Khaja Ahmad SHAIKKiyoo ITOHAmara AMARA
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2016 Volume E99.A Issue 2 Pages 523-530

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Abstract

To achieve low-voltage low-power SRAMs, two proposals are demonstrated. One is a multi-power-supply five-transistor cell (5T cell), assisted by a boosted word-line voltage and a mid-point sensing enabled by precharging bit-lines to VDD/2. The cell enables to reduce VDD to 0.5V or less for a given speed, or enhance speed for a given VDD. The other is a partial activation of a compact multi-divided open-bit-line array for low power. Layout and post-layout simulation with a 28-nm fully-depleted planar-logic SOI MOSFET reveal that a 0.5-V 5T-cell 4-kb array in a 128-kb SRAM core using the proposals is able to achieve x2-3 faster cycle time and x11 lower power than the counterpart 6T-cell array, suggesting a possibility of a 730-ps cycle time at 0.5V.

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© 2016 The Institute of Electronics, Information and Communication Engineers
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